Apparatus and method for timestamping of data packets

1. A communications device, comprising:

an input bit counter configured to maintain a first count responsive to input bits received by a physical layer (PHY) device from a media access control (MAC) sublayer;

an output bit counter configured to maintain a second count responsive to output bits transmitted by the PHY device onto a physical medium; and

control circuitry configured to:

upon receipt, by the PHY device from the MAC sublayer, of a first bit of a data packet, determine a number of bits awaiting transmission by the PHY device onto the physical medium based on the first count and the second count;

calculate a timestamp for the data packet based on the determined number of bits and a pre-determined bit transmission rate of the PHY device, wherein the timestamp indicates a time of transmission of the first bit of the data packet by the PHY device onto the physical medium; and

insert the timestamp into a timestamp field of the data packet.

2. The communications device of claim 1 , wherein the control circuitry is configured to subtract the second count from the first count to determine the number of bits awaiting transmission by the PHY device onto the physical medium.

3. The communications device of claim 1 , wherein the control circuitry is configured to:

divide the determined number of bits by the pre-determined bit transmission rate of the PHY device to determine a PHY latency for the first bit of the data packet; and

add the determined PHY latency to a current clock time to determine the timestamp for the data packet.

4. The communications device of claim 1 , wherein the input bits include a data block having a pre-defined number of bits, and wherein the control circuitry is further configured to:

determine a number of overhead bits that are added to the pre-defined number of bits of the data block due to processing by the PHY device before transmission onto the physical medium; and

control the input bit counter to increment the first count by the pre-defined number of bits of the data block adjusted by the number of overhead bits.

5. The communications device of claim 4 , wherein the number of overhead bits is responsive to one or more of: line encoding bits added to the data block, alignment marker insertion bits added to the data block, Forward Error Correction (FEC) compression bits removed from the data block, and FEC parity bits added to the data block.

6. The communications device of claim 1 , wherein the PHY device includes a plurality of transmission lanes, and wherein the input bit counter and the output bit counter correspond to a first transmission lane of the plurality of transmission lanes.

7. The communications device of claim 1 , wherein the input bit counter and the output bit counter are associated with different clock domains, the control circuitry further configured to:

compute a cross-domain transfer time error associated with transferring one or more of the first count and the second count to another clock domain; and

determine the number of bits awaiting transmission by the PHY device using the computed cross-domain transfer time error.

8. The communications device of claim 6 , further comprising:

a second input bit counter configured to maintain a third count responsive to input bits received by a second transmission lane of the PHY device from the MAC sublayer; and

a second output bit counter configured to maintain a fourth count responsive to output bits transmitted by the second transmission lane of the PHY device onto the physical medium.

9. A method of processing data packets, comprising:

receiving, by a physical layer (PHY) device, input bits including a data packet from a media access control (MAC) sublayer;

determining a number of bits awaiting transmission by the PHY device onto a physical medium based on a first count and a second count, the first count responsive to a number of the input bits that entered the PHY device, and the second count responsive to a number of bits transmitted by the PHY device onto the physical medium; and

calculating a timestamp for the data packet based on the determined number of bits awaiting transmission by the PHY device and a pre-determined bit transmission rate of the PHY device, wherein the timestamp indicates a time of transmission of the first bit of the data packet by the PHY device onto the physical medium;

inserting the timestamp into a timestamp field of the data packet; and

transmitting the data packet on to the physical medium using the PHY device.

10. The method of claim 9 , further comprising:

incrementing the first count responsive to the number of the input bits that entered the PHY device; and

incrementing the second count responsive to transmitting the data packet on the physical medium using the PHY device.

11. The method of claim 9 , wherein determining the number of bits awaiting transmission by the PHY device onto the physical medium comprises subtracting the second count from the first count.

12. The method of claim 9 , further comprising:

dividing the determined number of bits by the pre-determined bit transmission rate of the PHY device to determine a PHY latency for the first bit of the data packet; and

adding the determined PHY latency to a current clock time to calculate the timestamp for the data packet.

13. The method of claim 9 , wherein the input bits include a data block having a pre-defined number of bits, the method further comprising:

determining a number of overhead bits that are added to the pre-defined number of bits of the data block due to processing of the data block by the PHY device before transmission onto the physical medium; and

incrementing the first count responsive to receiving the data block by the pre-defined number of bits of the data block adjusted by the number of overhead bits.

14. The method of claim 13 , wherein the number of overhead bits is responsive to one or more of: line encoding bits added to the data block, alignment marker insertion bits added to the data block, Forward Error Correction (FEC) compression bits removed from the data block, and FEC parity bits added to the data block.

15. The method of claim 9 , further comprising:

computing a cross-domain transfer time error associated with transferring one or more of the first count and the second count to another clock domain; and

determining the number of bits awaiting transmission by the PHY device using the computed cross-domain transfer time error.

16. A communications device, comprising:

an input bit counter configured to maintain a first count responsive to input bits received by a physical layer (PHY) device from a media access control (MAC) sublayer;

an output bit counter configured to maintain a second count responsive to output bits transmitted by the PHY device onto a physical medium; and

control circuitry configured to:

upon receipt, by the PHY device from the MAC sublayer, of a first bit of a data packet, determine a number of bits awaiting transmission by the PHY device onto the physical medium based on the first count and the second count; and

calculate a timestamp for the data packet based on the determined number of bits and a pre-determined bit transmission rate of the PHY device, wherein the timestamp is at least partially calculated by dividing the determined number of bits by the pre-determined bit transmission rate of the PHY device to determine a PHY latency for the first bit of the data packet.

17. The communications device of claim 16 , wherein the control circuitry is further configured to add the determined PHY latency to a current clock time to determine the timestamp for the data packet.

18. The communications device of claim 17 , wherein the control circuitry is further configured to insert the timestamp into a timestamp field of the data packet for transmission of the data packet onto the physical medium by the PHY device.

19. The communications device of claim 16 , wherein the timestamp indicates a time of transmission of the first bit of the data packet by the PHY device onto the physical medium.

20. The communications device of claim 16 , wherein the PHY device includes a plurality of transmission lanes, and wherein the input bit counter and the output bit counter correspond to a first transmission lane of the plurality of transmission lanes, the communications device further comprising:

a second input bit counter configured to maintain a third count responsive to input bits received by a second transmission lane of the PHY device from the MAC sublayer; and

a second output bit counter configured to maintain a fourth count responsive to output bits transmitted by the second transmission lane of the PHY device onto the physical medium.