IP Library Granted Patent US 9,917,503
Granted Patent B2
US 9,917,503 · App. 15/154,094 · Granted Mar 13, 2018

Overcurrent protection circuit and power factor correction circuit comprising the same

Inventors: Taesung Kim (Incheon, KR); Gwanbon Koo (Bucheon-si, KR)
Assignee: Fairchild Korea Semiconductor Ltd.
H02M1/32H02M1/4258H02M3/33523Y02B70/126
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,917,503
App. No.
15/154,094
Granted
Mar 13, 2018
Kind
B2
Abstract

A power factor correction circuit includes an overcurrent protection circuit, and the overcurrent protection circuit detects at least one of a line input voltage, a switch current of a power factor correction circuit, and a line period peak and performs overcurrent protection operations using a detection result.

Claims (75)

1. A power factor correction circuit comprising:

a switch converting a line input voltage into output power; and

an overcurrent protection circuit limiting current of the switch during an overcurrent condition,

wherein the overcurrent protection circuit is configured to control a peak of the current of the switch to follow a sine wave in synchronization with the line input voltage during the overcurrent condition.

2. The power factor correction circuit of claim 1 , wherein the overcurrent protection circuit includes:

a first current source generating a first current according to a line period peak which is a period unit peak of the line input voltage;

a second current source generating a second current according to a line detection voltage corresponding to the line input voltage;

a comparator determining whether a first voltage increased by the first current source reaches an overcurrent protection threshold voltage; and

a capacitor receiving the second current according to an output of the comparator, and

the overcurrent protection circuit is synchronized with the output of the comparator and samples a voltage of the capacitor, thereby generating a regular overcurrent protection reference.

3. The power factor correction circuit of claim 2 , wherein the overcurrent protection circuit further includes:

a first capacitor including one end coupled to the first current source; and

a transistor coupled to the first capacitor in parallel, and

the transistor is switching-operated according to a clock signal having a predetermined period.

4. The power factor correction circuit of claim 2 , wherein the overcurrent protection circuit further includes:

a first transistor coupled between the second current source and the capacitor; and

a second transistor coupled to the capacitor in parallel, and

the first transistor is switching-operated according to the output of the comparator.

5. The power factor correction circuit of claim 2 , wherein the overcurrent protection circuit resets the first voltage according to a clock signal having a predetermined period, and samples a voltage of the capacitor according to the clock signal and a signal generated based on the output of the comparator.

6. The power factor correction circuit according to claim 1 , wherein the overcurrent protection circuit includes:

a peak detecting unit detecting a line period peak which is a line period unit peak of the line input voltage; and

a maximum on-time calculating unit setting an overcurrent reference voltage corresponding to an overcurrent reference for an overcurrent threshold period of time using a line period peak in a case in which a peak of the switch current is the same as a threshold value, and a PWM signal controlling switching operations of the switch, and calculating the maximum on-time according to a result of comparing a voltage generated based on the line period peak and the PWM signal and the overcurrent reference voltage, and

the overcurrent threshold period of time is a period of time in which the peak of the switch current is reached to the threshold value.

7. The power factor correction circuit according to claim 6 , wherein the maximum on-time calculating unit includes:

a current source generating a first current according to the line period peak for the overcurrent threshold period of time; and

a capacitor coupled to the current source, and

the maximum on-time calculating unit generates a first voltage by supplying the first current to the capacitor for a period of time according to the PWM signal, samples the first voltage, and generates the overcurrent reference voltage based on a minimum voltage of a voltage sampled for the overcurrent threshold period of time.

8. The power factor correction circuit according to claim 7 , wherein the maximum on-time calculating unit further includes:

a comparator comparing the first voltage and the sampled voltage; and

a logic gate controlling sampling operations according to the PWM signal and output of the comparator, and

in a case in which the first voltage is the sampled voltage or more, the logic gate disables the sampling operations according to the comparator output.

9. The power factor correction circuit according to claim 8 , wherein the maximum on-time calculating unit further includes:

a first capacitor charged by the first voltage through a first switch switching-operated according to the PWM signal; and

a second capacitor charged by a voltage of the first capacitor through a second switch switching-operated according to output of the logic gate, and

the comparator has a first input terminal coupled to one end of the first capacitor, and the comparator has a second input terminal coupled to one end of the second capacitor.

10. The power factor correction circuit according to claim 7 , wherein the maximum on-time calculating unit further includes a transistor coupled to the capacitor in parallel and switching-operated according to a signal in which the PWM signal is inverted, and

a sampling period of the first voltage is synchronized with the PWM signal.

11. The power factor correction circuit according to claim 7 , wherein the maximum on-time calculating unit generates the overcurrent reference voltage by multiplying the sampled voltage by a first ratio, and

the first ratio is a ratio of an overcurrent threshold voltage corresponding to the threshold value with respect to a predetermined overcurrent protection threshold voltage.

12. The power factor correction circuit according to claim 6 , wherein the maximum on-time calculating unit includes:

a current source generating a second current according to the line period peak after the overcurrent threshold period of time;

a capacitor coupled to the current source; and

a comparator comparing a voltage of the capacitor and the overcurrent reference voltage, and

the maximum on-time is determined according to output of the comparator.

13. The power factor correction circuit of claim 1 , wherein the overcurrent protection circuit is configured to control a peak of the sine wave to be constant by controlling a maximum on-time of the switch.

14. The power factor correction circuit of claim 13 , wherein the overcurrent protection circuit includes:

a peak detecting unit generating a detection voltage peak corresponding to the peak of the switch current by a line period unit of the line input voltage; and

a maximum on-time calculating unit setting an overcurrent reference voltage corresponding to an overcurrent reference using a predetermined overcurrent protection threshold voltage and a PWM signal controlling switching operations of the switch for a predetermined set period of time and calculating the_maximum on-time according to the detection voltage peak and the overcurrent reference voltage.

15. The power factor correction circuit of claim 14 , wherein the maximum on-time calculating unit includes:

a current source generating a first current according to the overcurrent protection threshold voltage for the set period of time; and

a capacitor coupled to the current source, and

the maximum on-time calculating unit generates a first voltage by supplying the first current to the capacitor for a period of time according to the PWM signal, and generates the overcurrent reference voltage by sampling the first voltage.

16. The power factor correction circuit of claim 15 , wherein the maximum on-time calculating unit further includes a transistor coupled to the capacitor in parallel, and switching-operated according to a signal in which the PWM signal is inverted, and a sampling period of the first voltage is synchronized with the PWM signal.

17. The power factor correction circuit of claim 14 , wherein the maximum on-time calculating unit includes:

a current source generating a second current according to the detection voltage peak not for the set period of time but for a non-set period of time;

a capacitor coupled to the current source; and

a comparator comparing the voltage of the capacitor and the overcurrent reference voltage, and

the maximum on-time is determined according to an output of the comparator.

18. The power factor correction circuit of claim 13 , wherein the overcurrent protection circuit includes:

a line voltage detecting unit generating a line detection voltage by detecting the line input voltage;

a peak detecting unit detecting a line period peak which is a line period unit peak of the line input voltage; and

a maximum on-time calculating unit setting an overcurrent reference voltage corresponding to an overcurrent reference using the line detection voltage and a PWM signal controlling switching operations of the switch for an overcurrent threshold period of time in which the peak of the switch current is the same as a threshold value, and calculating a maximum on-time according to a result of comparing a voltage generated based on the line period peak and the PWM signal and the overcurrent reference voltage.

19. The power factor correction circuit of claim 18 , wherein the maximum on-time calculating unit includes:

a current source generating a first current according to the line detection voltage for the overcurrent threshold period of time; and

a capacitor coupled to the current source, and

the maximum on-time calculating unit generates a first voltage by supplying the first current to the capacitor for a period of time according to the PWM signal, and generates the overcurrent reference voltage by sampling the first voltage.

20. The power factor correction circuit of claim 19 , wherein the maximum on-time calculating unit further includes a transistor coupled to the capacitor in parallel, and switching-operated according to a signal in which the PWM signal is inverted, and

a sampling period of the first voltage is synchronized with the PWM signal.

21. The power factor correction circuit of claim 19 , wherein the maximum on-time calculating unit generates the overcurrent reference voltage by multiplying the sampled voltage by a first ratio, and

the first ratio is a ratio of an overcurrent threshold voltage corresponding to the threshold value with respect to a predetermined overcurrent protection threshold voltage.

22. The power factor correction circuit according to claim 18 , wherein the maximum on-time calculating unit includes:

a current source generating a second current according to the line period peak after the overcurrent threshold period of time;

a capacitor coupled to the current source; and

a comparator comparing the voltage of the capacitor and the overcurrent reference voltage, and

the maximum on-time is determined according to an output of the comparator.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 04481, FRAME 0541 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064072/0459 →
PATENT SECURITY AGREEMENT Recorded Nov 17, 2017
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 044481/0541 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2017
From: FAIRCHILD KOREA SEMICONDUCTOR, LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 044361/0205 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 13, 2016
From: KIM, TAESUNG; KOO, GWANBON
To: FAIRCHILD KOREA SEMICONDUCTOR LTD
Reel/Frame 038585/0935 →
Continuity (2)
Provisional Application 62160876 · May 13, 2015
Related Publication 20160336847A1 · Nov 17, 2016