IP Library › Granted Patent US 10,091,749

Granted Patent B2

US 10,091,749 · App. 15/156,543 · Granted Oct 2, 2018

Reference signal generation redundancy in distributed antenna systems (DAS), and related devices and methods

Inventors: Dror Harel (Hod Hasharon, IL); Boris Radin (Ashdod, IL)

Assignee: Corning Optical Communications Wireless Ltd

H04W56/0015 H04B7/04 H04J3/0688 H04L7/0331 H04W24/02

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Quick Facts

Patent No.: US 10,091,749
App. No.: 15/156,543
Granted: Oct 2, 2018
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

Embodiments for providing reference signal generation redundancy in distributed antenna systems (DASs) are disclosed. To avoid a single point of failure in reference signal generation that could cause components relying on the reference signal to not operate properly, the reference signal generation circuits disclosed herein include a plurality of reference signal generation modules. One reference signal generation module is configured as the master reference signal generation module to generate a master reference signal distributed in the DAS. The other reference signal generation modules are configured as slave reference signal generation modules. If a failure is detected in the generation of the master reference signal in the master reference signal generation module, another slave reference signal generation module is reconfigured to be the new master reference signal generation module to generate the master reference signal. In this manner, the reference signal generation circuit does not have a single point of failure.

Claims (138)

1. A reference signal generation circuit for providing reference signal generation redundancy in a distributed antenna system (DAS), comprising:

a first reference signal generation module, comprising:

a first master oscillator configured to generate a first reference signal as a first master oscillator output;

a first detector coupled to the first master oscillator output, the first detector configured to:

detect the first reference signal generated by the first master oscillator; and

provide a first detection output representing a detection state of the first reference signal; and

a first reference signal switch configured to receive:

the first reference signal as a first input;

a second reference signal from a second reference signal generation module as a second input; and

a first switch control input representing the detection state of the first reference signal;

the first reference signal switch further configured to:

provide the first reference signal as a master reference signal on a first master reference signal generation module output to at least one first DAS component in a DAS based on the first switch control input representing detection of the first reference signal by the first detector; and

provide the second reference signal as the master reference signal on the first master reference signal generation module output to the at least one first DAS component in the DAS based on the first switch control input representing detection failure of the first reference signal by the first detector.

2. The reference signal generation circuit of claim 1 , wherein:

the first reference signal generation module further comprises a second detector coupled to the first master reference signal generation module output of the first reference signal switch, the second detector configured to:

detect the first master reference signal generation module output provided by the first reference signal switch; and

provide a second detection output representing a detection state of the first master reference signal generation module output.

3. The reference signal generation circuit of claim 2 , wherein:

the first reference signal generation module further comprises a third detector coupled to the second input of the first reference signal switch, the third detector configured to:

detect the second reference signal from the second reference signal generation module as the second input into the first reference signal switch; and

provide a third detection output representing a detection state of the second reference signal from the second reference signal generation module.

4. The reference signal generation circuit of claim 3 , wherein:

the first reference signal switch is further configured to provide the first reference signal as the master reference signal on the first master reference signal generation module output to the at least one first DAS component in the DAS based on the first switch control input representing detection of the first reference signal on the first master reference signal generation module output by the second detector, and detection failure of the second reference signal on the second input of the first reference signal switch by the third detector.

5. The reference signal generation circuit of claim 1 , wherein:

the first reference signal generation module further comprises a second detector coupled to the second input of the first reference signal switch, the second detector configured to:

detect the second reference signal from the second reference signal generation module as the second input into the first reference signal switch; and

provide a second detection output representing a detection state of the second reference signal from the second reference signal generation module.

6. The reference signal generation circuit of claim 1 , further comprising:

a second reference signal generation module, comprising:

a second oscillator configured to generate the second reference signal as a second oscillator output;

a second detector coupled to the second oscillator output, the second detector configured to:

detect the second reference signal generated by the second oscillator; and

provide a second detection output representing a detection state of the second reference signal; and

a second reference signal switch configured to receive:

the second reference signal as a first input;

the first reference signal from the first reference signal generation module as a second input; and

a second switch control input representing the detection state of the second reference signal;

the second reference signal switch further configured to:

provide the second reference signal as the master reference signal on a second reference signal generation module output to at least one second DAS component in the DAS based on the second switch control input representing detection of the second reference signal by the second detector; and

provide the first reference signal as the master reference signal on the second reference signal generation module output to the at least one second DAS component in the DAS based on the second switch control input representing detection failure of the second reference signal by the second detector.

7. The reference signal generation circuit of claim 6 , wherein:

the second reference signal generation module further comprises a third detector coupled to the second reference signal generation module output of the second reference signal switch, the third detector configured to:

detect the second reference signal generation module output provided by the second reference signal switch; and

provide a third detection output representing a detection state of the second reference signal generation module output.

8. The reference signal generation circuit of claim 7 , wherein:

the second reference signal generation module further comprises a fourth detector coupled to the second input of the second reference signal switch, the fourth detector configured to:

detect the first reference signal from the first reference signal generation module as the second input into the second reference signal switch; and

provide a fourth detection output representing a detection state of the first reference signal from the first reference signal generation module.

9. The reference signal generation circuit of claim 8 , wherein:

the second reference signal switch is further configured to provide the second reference signal as the master reference signal on the second reference signal generation module output to the at least one second DAS component in the DAS based on the second switch control input representing detection of the second reference signal on the second reference signal generation module output by the third detector, and detection failure of the first reference signal on the second input of the second reference signal switch by the fourth detector.

10. The reference signal generation circuit of claim 6 , wherein:

the second reference signal generation module further comprises a third detector coupled to the second input of the second reference signal switch, the third detector configured to:

detect the first reference signal from the first reference signal generation module as the second input into the second reference signal switch; and

provide a third detection output representing a detection state of the first reference signal from the first reference signal generation module.

11. The reference signal generation circuit of claim 6 , further comprising:

a first communications medium coupling the second reference signal generation module output to the second input of the first reference signal switch; and

a second communications medium coupling the first master reference signal generation module output to the second input of the second reference signal switch.

12. The reference signal generation circuit of claim 6 , further comprising a first higher frequency reference signal generation module, comprising:

a first higher frequency signal detector coupled to a first higher frequency reference signal generation module input, the first higher frequency signal detector configured to:

detect the master reference signal provided by the first reference signal generation module; and

provide a first higher frequency detection output representing a detection state of the master reference signal provided by the first reference signal generation module;

a second higher frequency signal detector coupled to a second higher frequency reference signal generation module input, the second higher frequency signal detector configured to:

detect the master reference signal provided by the second reference signal generation module; and

provide a second higher frequency detection output representing a detection state of the master reference signal provided by the second reference signal generation module; and

a first higher frequency signal switch configured to receive:

the master reference signal provided by the first reference signal generation module as a first input on the first higher frequency reference signal generation module input;

the master reference signal provided by the second reference signal generation module as a second input provided on the second higher frequency reference signal generation module input; and

a first higher frequency signal switch control input representing the detection state of the master reference signal provided by the first master reference signal generation module output detected by the first higher frequency signal detector and the detection state of the master reference signal provided by the second reference signal generation module output detected by the second higher frequency signal detector;

the first higher frequency signal switch further configured to:

provide a master higher frequency reference signal based on the master reference signal provided by the first reference signal generation module as a first higher frequency reference signal output, based on the first higher frequency signal switch control input representing detection of the master reference signal provided by the first reference signal generation module by the first higher frequency signal detector; and

provide the master higher frequency reference signal based on the master reference signal provided by the second reference signal generation module on the first higher frequency reference signal output, based on the first higher frequency signal switch control input representing detection failure of the master reference signal provided by the second reference signal generation module by the second higher frequency signal detector.

13. The reference signal generation circuit of claim 12 , wherein the first higher frequency reference signal generation module further comprises a first phase-locked-loop (PLL) module configured to receive the first higher frequency reference signal output and generate the master higher frequency reference signal as a first PLL higher frequency reference signal on a first PLL module output.

14. The reference signal generation circuit of claim 13 , wherein the first higher frequency reference signal generation module further comprises:

a second PLL module configured to receive the first higher frequency reference signal output and generate the master higher frequency reference signal as a second PLL higher frequency reference signal on a second PLL module output;

a first PLL detector coupled to the first PLL module output, the first PLL detector configured to:

detect the first PLL higher frequency reference signal generated by the first PLL module; and

provide a first PLL higher frequency detection output representing a detection state of the first PLL higher frequency reference signal generated by the first PLL module;

a second PLL detector coupled to the second PLL module output, the second PLL detector configured to:

detect the second PLL higher frequency reference signal generated by the second PLL module; and

provide a second PLL higher frequency detection output representing a detection state of the second PLL higher frequency reference signal generated by the second PLL module; and

a first PLL signal switch configured to receive:

the first PLL module output as a first input;

the second PLL module output as a second input; and

a first PLL module control input representing the detection state of the first PLL higher frequency reference signal provided by the first PLL module detected by the first PLL detector and the detection state of the second PLL higher frequency reference signal provided by the second PLL module detected by the second PLL detector;

the first PLL signal switch further configured to:

provide the first PLL higher frequency reference signal as the first higher frequency reference signal output, based on the first PLL module control input representing detection of the first PLL higher frequency reference signal generated by the first PLL module detected by the first PLL detector; and

provide the second PLL higher frequency reference signal as the first higher frequency reference signal output, based on the first PLL module control input representing detection failure of the first PLL higher frequency reference signal generated by the first PLL module detected by the first PLL detector.

15. The reference signal generation circuit of claim 12 , further comprising a second higher frequency reference signal generation module, comprising:

a third higher frequency signal detector coupled to a third higher frequency reference signal generation module input, the third higher frequency signal detector configured to:

detect the master reference signal provided by the second reference signal generation module; and

provide a third higher frequency detection output representing a detection state of the master reference signal provided by the second reference signal generation module;

a fourth higher frequency signal detector coupled to a fourth higher frequency reference signal generation module input, the fourth higher frequency signal detector configured to:

detect the master reference signal provided by the first reference signal generation module; and

provide a fourth higher frequency detection output representing a detection state of the master reference signal provided by the first reference signal generation module; and

a second higher frequency signal switch configured to receive:

the master reference signal provided by the second reference signal generation module as a first input on the third higher frequency reference signal generation module input;

the master reference signal provided by the first reference signal generation module as a second input provided on the fourth higher frequency reference signal generation module input; and

a second higher frequency signal switch control input representing the detection state of the master reference signal provided by the second reference signal generation module output detected by the third higher frequency signal detector and the detection state of the master reference signal provided by the first master reference signal generation module output detected by the fourth higher frequency signal detector;

the second higher frequency signal switch further configured to:

provide the master higher frequency reference signal based on the master reference signal provided by the second reference signal generation module as a second higher frequency reference signal output, based on the second higher frequency signal switch control input representing detection of the master reference signal provided by the first reference signal generation module by the third higher frequency signal detector; and

provide the master higher frequency reference signal based on the master reference signal provided by the first reference signal generation module on the second higher frequency reference signal output, based on the second higher frequency signal switch control input representing detection failure of the master reference signal provided by the second reference signal generation module by the fourth higher frequency signal detector.

16. The reference signal generation circuit of claim 15 , wherein the second higher frequency reference signal generation module further comprises a third phase-locked-loop (PLL) module configured to receive the second higher frequency reference signal output and generate the master higher frequency reference signal as a third PLL higher frequency reference signal on a third PLL module output.

17. The reference signal generation circuit of claim 16 , wherein the second higher frequency reference signal generation module further comprises:

a fourth PLL module configured to receive the second higher frequency reference signal output and generate the master higher frequency reference signal as a fourth PLL higher frequency reference signal on a fourth PLL module output;

a third PLL detector coupled to the third PLL module output, the third PLL detector configured to:

detect the third PLL higher frequency reference signal generated by the third PLL module; and

provide a third PLL higher frequency detection output representing a detection state of the third PLL higher frequency reference signal generated by the third PLL module;

a fourth PLL detector coupled to the fourth PLL module output, the fourth PLL detector configured to:

detect the fourth PLL higher frequency reference signal generated by the fourth PLL module; and

provide a fourth PLL higher frequency detection output representing a detection state of the fourth PLL higher frequency reference signal generated by the fourth PLL module; and

a second PLL signal switch configured to receive:

the third PLL module output as a first input;

the fourth PLL module output as a second input; and

a second PLL module control input representing the detection state of the third PLL higher frequency reference signal provided by the third PLL module detected by the third PLL detector and the detection state of the fourth PLL higher frequency reference signal provided by the fourth PLL module detected by the fourth PLL detector;

the second PLL signal switch further configured to:

provide the third PLL higher frequency reference signal as the second higher frequency reference signal output, based on the second PLL module control input representing detection of the third PLL higher frequency reference signal generated by the third PLL module detected by the third PLL, detector; and

provide the fourth PLL higher frequency reference signal as the second higher frequency reference signal output, based on the second PLL module control input representing detection failure of the third PLL higher frequency reference signal generated by the third PLL module detected by the third PLL detector.

18. The reference signal generation circuit of claim 12 , further comprising:

a third communications medium coupling the first master reference signal generation module output to the first higher frequency reference signal generation module input; and

a fourth communications medium coupling the second reference signal generation module output to the second higher frequency reference signal generation module input.

19. The reference signal generation circuit of claim 12 , wherein the first reference signal generation module and the first higher frequency reference signal generation module are provided in a same head-end unit equipment chassis.

20. The reference signal generation circuit of claim 12 , wherein the first reference signal generation module is provided in a first head-end unit equipment chassis and the first higher frequency reference signal generation module is provided in a second head-end unit equipment chassis different from the first head-end unit equipment chassis.

21. The reference signal generation circuit of claim 6 , further comprising:

a third reference signal generation module, comprising:

a third master oscillator configured to generate a third reference signal as a third master oscillator output;

a third detector coupled to the third master oscillator output, the third detector configured to:

detect the third reference signal generated by the third master oscillator; and

provide a third detection output representing a detection state of the third reference signal; and

a third reference signal switch configured to receive:

the third reference signal as a first input;

the second reference signal from the second reference signal generation module as a second input; and

a third switch control input representing the detection state of the third reference signal;

the third reference signal switch further configured to:

provide the third reference signal as the master reference signal on a third master reference signal generation module output to at least one third DAS component in the DAS based on the third switch control input representing detection of the third reference signal by the second detector; and

provide the second reference signal as the master reference signal on the third master reference signal generation module output to the at least one third DAS component in the DAS based on the third switch control input representing detection failure of the third reference signal by the third detector;

wherein the second reference signal from the second reference signal generation module as a second input to the first reference signal switch in the first reference signal generation module is comprised of the third reference signal from the third reference signal generation module.

22. The reference signal generation circuit of claim 6 , wherein the first reference signal generation module and the second reference signal generation module are provided in a same head-end unit equipment chassis.

23. The reference signal generation circuit of claim 6 , wherein the first reference signal generation module is provided in a first head-end unit equipment chassis and the second reference signal generation module is provided in a second head-end unit equipment chassis different from the first head-end unit equipment chassis.

Assignments (2)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 12, 2025

From: CORNING OPTICAL COMMUNICATIONS LLC

To: ANI ACQUISITION SUB, LLC

Reel/Frame 071270/0328 →

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 20, 2019

From: HAREL, DROR; RADIN, BORIS

To: CORNING OPTICAL COMMUNICATIONS LLC

Reel/Frame 050441/0857 →

Continuity (3)

Continuation PCTIL2014050967 · Nov 6, 2014

Provisional Application 61907746 · Nov 22, 2013

Related Publication 20160270016A1 · Sep 15, 2016