IP Library Granted Patent US 9,836,247
Granted Patent B2
US 9,836,247 · App. 15/157,310 · Granted Dec 5, 2017

Image processing semiconductor device and image processing device

Inventors: Hideaki Kido (Hitachi, JP); Shoji Muramatsu (Hitachinaka, JP); Hiroyuki Hamasaki (Kanagawa, JP); Akihiro Yamamoto (Kanagawa, JP)
Assignee: Renesas Electronics Corporation
G06F3/0659G06F3/0604G06F3/0673G06F9/30087G06K9/00805
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Quick Facts
Patent No.
US 9,836,247
App. No.
15/157,310
Granted
Dec 5, 2017
Kind
B2
Abstract

Provided is an image processing device capable of an image processing with using a general-purpose image processing hardware in accordance with video input without mediation of a CPU. The image processing device includes: a storage medium for storing an image data acquired by video inputting unit for acquiring video images; a CPU for a general processing; image processing unit for processing the image data stored in the storage medium; setting unit for determining a processing content of the image processing unit; a command list indicating an order of setting and activating the image processing unit; and command writing unit for setting and activating the image processing unit based on the command list in synchronization with input of the image data from the video inputting unit without mediation of the CPU.

Claims (22)

1. An image processing semiconductor device comprising:

a central processing unit (CPU);

an image processing circuit configured to process video image data acquired by a video inputting circuit and stored in a storage medium; and

a command writing circuit configured to activate the image processing circuit in response to receiving a notification from the video inputting circuit that the acquisition of the video image data is complete,

wherein the CPU does not receive the notification from the video inputting circuit that the acquisition of the video image data is complete.

2. An image processing device comprising:

a storage medium configured to store video image data acquired by a video inputting circuit;

a central processing unit (CPU);

an image processing circuit configured to process the video image data stored in the storage medium, the image processing circuit including a setting circuit configured to determine a processing content of the image processing circuit; and

a command writing circuit configured to set and activate the image processing circuit based on a synchronization signal, received from the video inputting circuit, indicating that the acquisition of the video image data is complete,

wherein the CPU does not receive the synchronization signal from the video inputting circuit indicating that the acquisition of the video image data is complete.

3. A method for image processing, comprising:

providing a central processing unit (CPU), an image processing circuit, and a command writing circuit;

processing, with the image processing circuit, video image data acquired by a video inputting circuit and stored in a storage medium; and

operating the command writing circuit to activate the image processing circuit in response to receiving a notification from the video inputting circuit that the acquisition of the video image data is complete,

wherein the CPU does not receive the notification from the video inputting circuit that the acquisition of the video image data is complete.

4. A method for image processing, comprising:

providing a storage medium, a central processing unit (CPU), an image processing circuit having a setting circuit, and a command writing circuit,

storing, in the storage medium, video image data acquired by a video inputting circuit;

processing, with the image processing circuit, the video image data stored in the storage medium, the setting circuit determining a processing content of the image processing circuit; and

operating the command writing circuit to set and activate the image processing circuit based on a synchronization signal, received from the video inputting circuit, indicating that the acquisition of the video image data is complete,

wherein the CPU does not receive the synchronization signal from the video inputting circuit indicating that the acquisition of the video image data is complete.

Assignments (1)
CHANGE OF ADDRESS Recorded Dec 7, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044742/0288 →
Priority Claims (1)
JP 2009-252856 · Nov 4, 2009 · national
Continuity (2)
Continuation 12917840 · Nov 2, 2010
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