Display device having a fall timing of a gate-on voltage that differs from a fall timing of a last pulse signal

1. A display apparatus comprising:

an image display region having a plurality of pixels sectioned by a plurality of scanning signal lines and a plurality of video signal lines; and

outside regions disposed outside of the image display region, the outside regions comprising:

a plurality of scanning connecting lines connected to the scanning signal lines, plural ones of the scanning signal lines being connected to one of the scanning connecting lines;

a plurality of thin film transistors including first thin film transistors, a source electrode and a drain electrode of each of the first thin film transistors being connected to a corresponding one of the scanning signal lines and a corresponding one of the scanning connecting lines;

a plurality of selection signal lines connected to gate electrodes of the first thin film transistors, plural ones of the first thin film transistors being connected to different ones of the scanning connecting lines and being connected to one of the selection signal lines; and

a scanning signal drive circuit connected to the scanning connecting lines and the selection signal lines, wherein

the scanning signal drive circuit performs a normal scanning mode in which pulse signals are supplied in turn to plural ones of the plurality of scanning connecting lines connected to the one of the plurality of selection signal lines, during a selection period in which a gate-on voltage is applied to one of the plurality of selection signal lines, gate-off voltages are applied to other ones of the plurality of selection signal lines, and

in the normal scanning mode, a fall timing of the gate-on voltage differs from a fall timing of a last one of the pulse signals supplied to the plural ones of the plurality of scanning connecting lines during the selection period.

2. The display apparatus according to claim 1 , wherein the last one of the pulse signals falls before the gate-on voltage falls.

3. The display apparatus according to claim 1 , wherein

the scanning signal drive circuit:

generates a first clock signal and a second clock signal having a same cycle as the first clock signal and having rise and fall timings different from those of the first clock signal; and

controls rise and fall of the gate-on voltage based on the first clock signal, and controls rise and fall of the pulse signals based on the second clock signal.

4. The display apparatus according to claim 1 , wherein

the selection signal lines include a first selection signal line and a second selection signal line, and

the scanning signal drive circuit:

switches, during a vertical scanning retrace period, between the normal scanning mode and a reset mode in which a gate-off voltage is applied to one of the selection signal lines, gate-on voltages are applied to other ones of the selection signal lines, and low-level voltages are applied to the scanning connecting lines; and

makes a timing at which a voltage applied to the first selection signal line is switched different from a timing at which a voltage applied to the second selection signal line is switched, when the scanning signal drive circuit switches between the normal scanning mode and the reset mode.

5. The display apparatus according to claim 4 , wherein, when the scanning signal drive circuit switches between the normal scanning mode and the reset mode, the scanning signal drive circuit makes timings at which the voltages applied to the plurality of selection signal lines are switched different from each other.

6. The display apparatus according to claim 4 , wherein

the scanning connecting lines, the first thin film transistors, and the selection signal lines are provided on both sides of the scanning signal lines, and

the scanning signal drive circuit:

performs the normal scanning mode on one of the sides and performs the reset mode on an other one of the sides; and

applies the gate-on voltage to each of the selection signal lines connected to the first thin film transistors connected to the one of the sides of the scanning signal lines, and applies the gate-off voltage to each of the selection signal lines connected to the first thin film transistors connected to the other one of the sides of the scanning signal lines.

7. The display apparatus according to claim 4 , wherein

the scanning connecting lines, the first thin film transistors, and the selection signal lines are provided on both sides of the scanning signal lines, and

the scanning signal drive circuit:

switches, during the vertical scanning retrace period, between a state in which the normal scanning mode is performed on one of the sides and the reset mode is performed on an other one of the sides, and a state in which the reset mode is performed on the one of the sides and the normal scanning mode is performed on the other one of the sides;

switches voltages applied to the plurality of selection signal lines on the one of the sides in turn during a first period included in the vertical scanning retrace period; and

switches voltages applied to the plurality of selection signal lines on the other one of the sides in turn during a second period included in the vertical scanning retrace period, and

the first period does not overlap the second period.

8. The display apparatus according to claim 1 , wherein

the scanning signal drive circuit performs a reset mode in which a gate-off voltage is applied to one of the plurality of selection signal lines, gate-on voltages are applied to other ones of the selection signal lines, and low-level voltages are applied to the scanning connecting lines, and

in the reset mode, a voltage applied to each of the selection signal lines is switched from the gate-off voltage to a higher voltage than the gate-on voltage and is then switched to the gate-on voltage.