Page programming sequences and assignment schemes for a memory device
Embodiments of the invention are directed towards a memory device comprising a plurality of wordlines each coupled to a row of memory cells in a subtile of the memory device, a plurality of level one column select circuits coupled to each cell in a plurality of groups of cells in a subtile, a plurality of level two column select circuits coupled to each of the plurality of groups of cells in the subtile, a common bit line coupled to the plurality of level one column select circuits and the plurality of level two column select circuits, the common bit line also coupled to a sense and program circuit, wherein the sense and program circuit addresses each first cell in each of the groups of cells to form a single page of memory.
1. A memory device comprising:
a plurality of sub-tiles in a memory section configured to include a plurality of memory cells;
a plurality of wordlines each configured to couple to a row of memory cells in the sub-tile; and
a column select circuit configured to control at least two level column lines;
a common bit line (CBL) coupled to the column select circuit, the common bit line also coupled to a sense and program circuit;
a common source line (CSL) coupled to the memory section,
wherein a selected time of one of the two level column lines is different from that of the other of the two level column lines, and
a pulse of the common source line is set to a low voltage for a reset operation.
2. The memory device of claim 1 , wherein the sense and program circuit addresses each first memory cell in groups of the plurality of memory cells to form a single page of memory for the reset operation.
3. The memory device of claim 1 , wherein a pulse of the common bit line for the reset operation is different from a pulse of the common bit line for a set operation.
4. The memory device of claim 1 , wherein the common source line (CSL) is set to a high voltage for a set operation.