IP Library Granted Patent US 9,946,125
Granted Patent B2
US 9,946,125 · App. 15/162,110 · Granted Apr 17, 2018

Liquid crystal display device

Inventors: Tomohide Onogi (Azumino, JP); Yasuo Segawa (Azumino, JP)
Assignee: Japan Display Inc.
G02F1/134336G02F1/1368G02F1/13439G02F1/133345G02F1/134363G02F1/136227G02F1/136286G02F2001/133357G02F2001/134372G02F2001/136295G02F2201/40G02F2202/103G02F2202/104
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Quick Facts
Patent No.
US 9,946,125
App. No.
15/162,110
Granted
Apr 17, 2018
Kind
B2
Abstract

A liquid crystal display device according to FFS technology is capable of providing a common electrode with common electric potential. A pixel electrode is formed of a first layer transparent electrode. A common electrode made of a second layer transparent electrode is formed above the pixel electrode interposing an insulation film between them. The common electrode in an upper layer is provided with a plurality of slits. The common electrode extends over all the pixels in a display region. An end of the common electrode is disposed on a periphery of the display region and connected with a peripheral common electric potential line that provides a common electric potential Vcom. There is provided neither an auxiliary common electrode line nor a pad electrode, both of which are provided in a liquid crystal display device according to a conventional art.

Claims (58)

1. A display device comprising:

a substrate;

a transparent electrode;

a plurality of pixels arranged in a matrix in a display portion on the substrate, each of the pixels having a pixel electrode overlapping the transparent electrode;

a common line arranged between the substrate and the transparent electrode, the common line being a metal line;

a layer interposed between the pixel electrode and the transparent electrode; and

a signal line having a first portion, a second portion, and a third portion,

wherein the second portion is arranged between the common line and the substrate and intersects with the common line in a planer view,

wherein the first portion, the second portion, and the third portion are electrically connected,

wherein the common line is electrically connected to the transparent electrode and

wherein the common line is arranged along four sides of the display portion in a planer view.

2. The display device according to claim 1 , wherein the third portion of the signal line comprises a same layer as the first portion.

3. The display device according to claim 1 , wherein

the third portion of the signal line is surrounded by the common line, and a voltage is applied to the signal line.

4. The display device according to claim 1 , wherein

the common line has four sides each arranged along each of the four sides of the display portion,

the transparent electrode is electrically connected to the four sides of the common line through a plurality of the first contacts.

5. The display device according to claim 1 , further comprising:

a plurality of thin film transistors in the pixels in the display portion;

a plurality of gate lines electrically connected to the thin film transistors; and

a gate line control circuit configured to provide a gate signal to each of the gate lines.

6. The display device according to claim 1 , further comprising:

a plurality of thin film transistors in the pixels in the display portion;

a plurality of signal lines electrically connected to the thin film transistors; and

a plurality of gate lines electrically connected to the thin film transistors;

wherein the first portion and the third portion of the signal line are in a same layer, and

wherein the second portion of the signal line is in a same layer as the gate lines.

7. The display device according to claim 1 , wherein the common line and the first contact are disposed outside the display portion.

8. A display device comprising:

a substrate a comprising:

an insulating surface;

a plurality of pixels arranged in a matrix in a display portion on the insulating surface, each of the pixels including a pixel electrode;

a transparent electrode that overlaps the pixel electrodes;

a layer interposed between the pixel electrodes and the transparent electrode; and

a common line that is disposed between the insulating surface of the substrate and the layer and that is connected to the transparent electrode, the common line being a metal line;

a signal line that intersects the common line in planar view and that is applied with a predetermined voltage, the signal line including:

a first portion;

a second portion that is arranged farther apart from the transparent electrode than the first portion; and

a third portion,

wherein

the first portion, the second portion, and the third portion are electrically connected,

the common line is disposed outside the display portion, and

the common line is arranged along four sides of the display portion in planar view.

9. The display device according to claim 8 , wherein the third portion of the signal line comprises at a same layer as the first portion.

10. The display device according to claim 8 , wherein the common line is disposed between the common electrode and the insulating surface of the substrate.

11. The display device according to claim 8 , wherein:

the common line has four sides each arranged along each of the four sides of the display portion, and

the transparent electrode is electrically connected to the four sides of the common line.

12. The display device according to claim 8 , further comprising:

a plurality of thin film transistors in the pixels in the display portion;

a plurality of gate lines electrically connected to the thin film transistors; and a gate line control circuit that provides a gate signal to each of the gate lines.

13. The display device according to claim 8 , further comprising:

a plurality of thin film transistors in the pixels in the display portion;

a plurality of signal lines electrically connected to the thin film transistors; and

a plurality of gate lines electrically connected to the thin film transistors;

wherein

the first portion and the third portion of the signal line are in a same layer, and

the second portion of the signal line is in a same layer as the gate lines.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 072130/0313 →
CHANGE OF NAME Recorded Sep 26, 2016
From: JAPAN DISPLAY WEST INC.
To: JAPAN DISPLAY INC.
Reel/Frame 040146/0765 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 26, 2016
From: ONOGI, TOMOHIDE; SEGAWA, YASUO
To: EPSON IMAGING DEVICES CORPORATION
Reel/Frame 039855/0933 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 26, 2016
From: EPSON IMAGING DEVICES CORPORATION
To: SONY CORPORATION
Reel/Frame 039856/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 26, 2016
From: SONY CORPORATION
To: JAPAN DISPLAY WEST INC.
Reel/Frame 039856/0030 →
Priority Claims (1)
JP 2006-204624 · Jul 27, 2006 · national
Continuity (2)
Continuation 11878579 · Jul 25, 2007
Related Publication 20160266453A1 · Sep 15, 2016