Pin cadence for high-speed connectors
A connector includes pins having a pinout including a functional designation cadence. The functional designation cadence includes a first ground pin, a first signal pin, a no-connect pin, a second signal pin, and a second ground pin, where the first signal pin is positioned between the first ground pin and the no-connect pin, the no-connect pin is positioned between the first and second signal pins, and the second signal pin is positioned between the no-connect pin and the second ground pin. Alternately, the functional designation cadence includes a first ground pin, a first signal pin, a third ground pin, a second signal pin, and a second ground pin, where the first signal pin is positioned between the first and third ground pins, the third ground pin is positioned between the first and second signal pins, and the second signal pin is positioned between the third and second ground pins.
1. A host connector that is configured for communication of data between a host system and a connector, the host connector comprising:
a plurality of pins having a complementary pinout to that of the connector, the complementary pinout including at least one functional designation cadence including:
a first ground pin, a first signal pin, a no-connect pin, a second signal pin, and a second ground pin, wherein the first signal pin is positioned between the first ground pin and the no-connect pin, the no-connect pin is positioned between the first signal pin and the second signal pin, and the second signal pin is positioned between the no-connect pin and the second ground pin; or
a first ground pin, a first signal pin, a third ground pin, a second signal pin, and a second ground pin, wherein the first signal pin is positioned between the first ground pin and the third ground pin, the third ground pin is positioned between the first signal pin and the second signal pin, and the second signal pin is positioned between the third ground pin and the second ground pin.
2. The host connector of claim 1 , wherein the functional designation cadence is repeated at least two times in the complementary pinout.
3. The host connector of claim 1 , wherein the first signal pin and the second signal are configured to carry a differential electrical signal.
4. The host connector of claim 3 , wherein the differential electrical signal includes a data rate of about 10 gigabits/second or higher.
5. The host connector of claim 1 , wherein the no-connect pin or the third ground pin is used during active alignment as a direct current output from an integrated circuit included in the connector.
6. The host connector of claim 1 , wherein the plurality of pins comprises forty-one pins.
7. The host connector of claim 6 , wherein the forty-one pins include the functional designation cadence repeated six times.
8. The host connector of claim 7 , wherein each of the six corresponding subsets of pins is configured to communicate a high-speed differential electrical signal to or from a corresponding one of six optical components included in the connector.
9. The host connector of claim 1 , wherein the plurality of pins includes at least one power pin.
10. The host connector of claim 9 , wherein the at least one power pin includes two power pins.
11. The host connector of claim 10 , wherein the two power pins are the center two pins.
12. The host connector of claim 1 , wherein the plurality of pins includes nine pines that are used for a two-wire interface with the connector.
13. The host connector of claim 1 , wherein the plurality of pins have a constant pitch of about 0.5 millimeters.
14. The host connector of claim 1 , further comprising a host printed circuit board that includes a plurality of electrical traces that contact the plurality of pins.
15. The host connector of claim 14 , wherein the host printed circuit board comprises a first via coupling the first ground pin to an electrical ground and a second via coupling the second ground pin to the electrical ground.
16. The host connector of claim 15 , wherein the host system includes a television, a monitor, or a media box.
17. The host connector of claim 1 , wherein:
the first signal pin is separated from the first ground pin by a pitch;
the first signal pin is separated from the second signal pin by two times the pitch; and
the second signal pin is separated from the second ground pin by the pitch.