Quantum computing in a three-dimensional device lattice
In a general aspect, information is encoded in data qubits in a three-dimensional device lattice. The data qubits reside in multiple layers of the three-dimensional device lattice, and each layer includes a respective two-dimensional device lattice. A three-dimensional color code is applied in the three-dimensional device lattice to detect errors in the data qubits residing in the multiple layers. A two-dimensional color code is applied in the two-dimensional device lattice in each respective layer to detect errors in one or more of the data qubits residing in the respective layer.
1. A method comprising:
encoding information in data qubits in a three-dimensional device lattice, the data qubits residing in multiple layers of the three-dimensional device lattice, each layer comprising a respective two-dimensional device lattice;
by operation of a control system, applying a three-dimensional color code in the three-dimensional device lattice to detect errors in one or more of the data qubits residing in the multiple layers; and
by operation of the control system, applying a two-dimensional color code in the two-dimensional device lattice in each respective layer to detect errors in one or more of the data qubits residing in the respective layer,
wherein a signal delivery system transfers signals between the three-dimensional device lattice and the control system.
2. The method of claim 1 , wherein applying the three-dimensional color code comprises operating ancilla qubits.
3. The method of claim 2 , wherein each of the ancilla qubits operates on a respective face of the three-dimensional color code.
4. The method of claim 2 , wherein each of the ancilla qubits operates on a respective edge of the three-dimensional color code.
5. The method of claim 1 , wherein the three-dimensional color code and the two-dimensional color code are applied to operate the data qubits in a universal fault-tolerant quantum computing regime.
6. The method of claim 1 , wherein each of the multiple layers comprises a three-colorable, three-valent arrangement of at least a subset of the data qubits.
7. The method of claim 6 , wherein each of the multiple layers comprises the same three-colorable, three-valent arrangement.
8. The method of claim 1 , wherein the three-dimensional device lattice comprises a four-colorable, four-valent arrangement of the data qubits, the two-dimensional device lattice of each layer comprises a three-colorable, three-valent arrangement of at least a subset of the data qubits in the layer, and the three-dimensional device lattice further comprises ancilla qubits in each layer.
9. A quantum computing system comprising:
a quantum processor cell comprising a three-dimensional device lattice comprising multiple layers of qubit devices, each layer comprising a respective two-dimensional device lattice, the three-dimensional device lattice comprising a four-colorable, four-valent arrangement of the qubit devices, the two-dimensional device lattice of each layer comprising a three-colorable, three-valent arrangement of a subset of the qubit devices in the layer;
a control system configured to:
encode information in data qubits in the three-dimensional device lattice, the data qubits residing in the multiple layers;
apply a three-dimensional color code in the three-dimensional device lattice to detect errors in one or more of the data qubits residing in the multiple layers; and
apply a two-dimensional color code in the two-dimensional device lattice in each respective layer to detect errors in one or more of the data qubits residing in the respective layer; and
a signal delivery system configured to transfer signals between the three-dimensional device lattice and the control system.
10. The quantum computing system of claim 9 , wherein the qubit devices comprise data qubit devices, and the quantum processor cell further comprises ancilla qubit devices.
11. The quantum computing system of claim 10 , wherein each of the ancilla qubit devices is configured to operate in a respective face of a three-dimensional color code.
12. The quantum computing system of claim 10 , wherein each of the ancilla qubit devices is configured to operate in a respective edge of a three-dimensional color code.
13. The quantum computing system of claim 9 , wherein the quantum processor cell comprises a superconducting quantum circuit that includes the qubit devices.
14. The quantum computing system of claim 9 , wherein each of the layers comprises the same three-colorable, three-valent arrangement.
15. A quantum computing system comprising:
a three-dimensional device lattice comprising multiple layers of data qubit devices, each layer comprising a respective two-dimensional device lattice;
a control system configured to:
encode information in data qubit devices in the three-dimensional device lattice;
apply a three-dimensional color code in the three-dimensional device lattice to detect errors in one or more of the data qubit devices residing in the multiple layers; and
apply a two-dimensional color code in the two-dimensional device lattice in each respective layer to detect errors in one or more of the data qubit devices residing in the respective layer; and
a signal delivery system configured to transfer signals between the three-dimensional device lattice and the control system.
16. The quantum computing system of claim 15 , wherein the three-dimensional device lattice comprises a four-colorable, four-valent arrangement of the data qubit devices, the two-dimensional device lattice of each layer comprises a three-colorable, three-valent arrangement of a subset of the data qubit devices in the layer, and the three-dimensional device lattice further comprises ancilla qubit devices in each layer.
17. The quantum computing system of claim 15 , wherein the three-dimensional device lattice comprises ancilla qubit devices, and applying the three-dimensional color code includes operating the ancilla qubit devices.
18. The quantum computing system of claim 15 , comprising a quantum processor cell, wherein the three-dimensional device lattice is housed in the quantum processor cell.
19. The quantum computing system of claim 18 , wherein the three-dimensional device lattice comprises a sub-lattice of a larger three-dimensional device lattice housed in the quantum processor cell.