Encapsulated dies with enhanced thermal performance
The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.
1. An apparatus comprising:
a carrier having a top surface;
an etched flip chip die from which at least a portion of a substrate has been removed, and comprising a device layer attached to the top surface of the carrier;
a first mold compound residing on the top surface of the carrier, surrounding the etched flip chip die, and extending beyond a top surface of the etched flip chip die to form a cavity within the first mold compound, wherein the top surface of the etched flip chip die is exposed at a bottom of the cavity; and
a second mold compound filling the cavity and in contact with the top surface of the etched flip chip die, wherein:
the etched flip chip die comprises no substrate over the device layer, such that the top surface of the etched flip chip die in contact with the second mold compound is a top surface of the device layer; or
the etched flip chip die comprises a residual portion of the substrate over the device layer, such that the top surface of the etched flip chip die in contact with the second mold is a top surface of the residual portion of the substrate, wherein the residual portion of the substrate has a thickness less than 25 μm.
2. The apparatus of claim 1 wherein no residual substrate resides over the device layer.
3. The apparatus of claim 1 wherein the residual portion of the substrate with a thickness less than 25 μm resides over the device layer.
4. The apparatus of claim 1 wherein the second mold compound further resides over the first mold compound.
5. The apparatus of claim 1 wherein a top surface of the second mold compound is planarized.
6. The apparatus of claim 1 wherein the second mold compound has high thermal conductivity between 2.5 w/m·k and 10 w/m·k.
7. The apparatus of claim 1 wherein the second mold compound has a thermal conductivity greater than 2.5 w/m·k.
8. The apparatus of claim 1 wherein the second mold compound has a thermal conductivity greater than 10 w/m·k.
9. The apparatus of claim 1 wherein the carrier is one of a group consisting of a laminate, a wafer level fan out (WLFO) carrier, a lead frame, and a ceramic carrier.
10. The apparatus of claim 1 wherein the first mold compound is an organic epoxy resin system.
11. The apparatus of claim 1 wherein the device layer includes at least one of a group consisting of diodes, transistors, mechanical switches, and resonators.
12. The apparatus of claim 1 wherein a thickness of the device layer is 4-7 μm.
13. The apparatus of claim 1 wherein the first mold compound and the second mold compound are formed from different materials.
14. The apparatus of claim 13 wherein the second mold compound has a thermal conductivity between 2.5 w/m·k and 10 w/m·k.
15. The apparatus of claim 13 wherein the second mold compound has a thermal conductivity greater than 2.5 w/m·k.
16. The apparatus of claim 13 wherein the second mold compound has a thermal conductivity greater than 10 w/m·k.
17. The apparatus of claim 1 wherein the device layer and the residual portion of the substrate together are no more than 32 μm thick.
18. The apparatus of claim 1 wherein the cavity has a deepness at least 142.5 μm.
19. The apparatus of claim 1 wherein the etched flip chip die further comprises a layer contact and a solder interconnection, wherein:
the layer contact is on a bottom surface of the device layer, which is opposite the cavity;
the solder interconnection connects the layer contact and the carrier.