Anti-fuse type nonvolatile memory cells, arrays thereof, and methods of operating the same
An anti-fuse type nonvolatile memory cell includes a semiconductor layer having a first conductivity type, a junction region having a second conductivity type and a trench isolation layer disposed in an upper portion of the semiconductor layer spaced apart from each other by a channel region, an anti-fuse insulation pattern disposed on the channel region, a gate electrode disposed on the anti-fuse insulation pattern, a gate spacer disposed on sidewalls of the anti-fuse insulation pattern and the gate electrode, a word line connected to the gate electrode, and a bit line connected to the junction region. The anti-fuse insulation pattern is broken if a first bias voltage and a second bias voltage are applied to the word line and the bit line, respectively.
1. An anti-fuse type nonvolatile memory (NVM) cell comprising:
a semiconductor layer having a first conductivity type;
a junction region having a second conductivity type and a trench isolation layer disposed in an upper portion of the semiconductor layer spaced apart from each other by a channel region;
an anti-fuse insulation pattern disposed on the channel region;
a gate electrode disposed on the anti-fuse insulation pattern, the gate electrode being comprised of a polysilicon material doped with impurities having the second conductivity type;
a gate spacer disposed on sidewalls of the anti-fuse insulation pattern and the gate electrode;
a word line connected to the gate electrode; and
a bit line connected to the junction region,
wherein the anti-fuse insulation pattern is broken when a first bias voltage and a second bias voltage are applied to the word line and the bit line, respectively, and the gate electrode, the semiconductor layer and the junction region constitute a bipolar junction transistor when the anti-fuse insulation pattern is broken.
2. The anti-fuse type NVM cell of claim 1 , wherein the first conductivity type is P-type and the second conductivity type is N-type.
3. The anti-fuse type NVM cell of claim 1 , wherein the gate electrode is spaced apart from the junction region in a horizontal direction by a lower width of the gate spacer adjacent to a surface of the channel region.
4. The anti-fuse type NVM cell of claim 3 , wherein the gate electrode extends onto the trench isolation layer.
5. The anti-fuse type NVM cell of claim 3 , wherein the junction region is aligned with an outer sidewall of the gate spacer disposed on a sidewall of the gate electrode adjacent to the junction region.
6. The anti-fuse type NVM cell of claim 1 , further comprising a metal silicide layer disposed on the junction region.
7. The anti-fuse type NVM cell of claim 1 ,
wherein the first bias voltage applied to the word line is higher than a threshold voltage for forming an inversion layer in the channel region and a breakdown voltage for breaking the anti-fuse insulation pattern, and
wherein the second bias voltage applied to the bit line is a ground voltage.