Thermal management for photonic integrated circuits
Embodiments of the invention describe apparatuses, systems, and methods of thermal management for photonic integrated circuits (PICs). Embodiments include a first device and a second device comprising including waveguides, wherein the first and second devices have different thermal operating conditions. A first region is adjacent to a waveguide of the first device, wherein its optical mode is to be substantially confined by the first region, and wherein the first region has a first thermal conductivity to dissipate heat based on the thermal operating condition of the first device. A second region is adjacent to a waveguide of the second device, wherein its optical mode is to be substantially confined by the second region, and wherein the second region has a second thermal conductivity to dissipate heat based on the thermal operating condition of the second device. In some embodiments, thermal cross talk is reduced without significantly affecting optical performance.
1. A layered photonic integrated circuit, comprising:
a substrate including a buried oxide layer, the buried oxide layer having a top surface that defines a plane extending in a lateral direction;
a first waveguide positioned on a top side of the plane;
a first region laterally aligned with the first waveguide and having a first thermal conductivity;
a second waveguide positioned on the top side of the plane and laterally offset from the first waveguide; and
a second region laterally aligned with the second waveguide and having a second thermal conductivity different from the first thermal conductivity, wherein one of the first or second regions extends at least partially through the buried oxide layer toward the plane.
2. The layered photonic integrated circuit of claim 1 , wherein the first region extends only partially through the buried oxide layer toward the plane.
3. The layered photonic integrated circuit of claim 1 , wherein the first region extends fully through the buried oxide layer to the plane.
4. The layered photonic integrated circuit of claim 1 , wherein the first region extends laterally beyond opposing lateral edges of the first waveguide.
5. The layered photonic integrated circuit of claim 1 , wherein the second region extends only partially through the buried oxide layer toward the plane.
6. The layered photonic integrated circuit of claim 1 , wherein the second region extends fully through the buried oxide layer to the plane.
7. The layered photonic integrated circuit of claim 1 , wherein the second waveguide comprises:
a silicon semiconductor layer disposed on the top side of the plane;
a cladding layer disposed on the silicon semiconductor layer; and
a III-V semiconductor layer disposed on the cladding layer.
8. The layered photonic integrated circuit of claim 7 , wherein the cladding layer further extends over the first waveguide.
9. The layered photonic integrated circuit of claim 8 , wherein the cladding layer further laterally surrounds opposing lateral edges of the first waveguide.
10. The layered photonic integrated circuit of claim 9 , wherein the cladding layer further contacts the buried oxide layer at locations away from the first and second waveguides.
11. The layered photonic integrated circuit of claim 1 , wherein the first waveguide comprises a passive optical device.
12. The layered photonic integrated circuit of claim 11 , wherein the first region is an unfilled cavity.
13. The layered photonic integrated circuit of claim 11 , wherein the first region includes a material having a low thermal conductivity.
14. The layered photonic integrated circuit of claim 13 , wherein the first region includes a dielectric material.
15. The layered photonic integrated circuit of claim 14 , wherein the dielectric material has a refractive index less than a refractive index of the first waveguide.
16. The layered photonic integrated circuit of claim 1 , wherein the second waveguide comprises an active optical device.
17. The layered photonic integrated circuit of claim 16 , wherein the second region includes a material having a high thermal conductivity.
18. The layered photonic integrated circuit of claim 17 , wherein the second region includes a metallic material.
19. A method of manufacturing a layered photonic integrated circuit, the method comprising:
forming a substrate including a buried oxide layer, the buried oxide layer having a top surface that defines a plane extending in a lateral direction;
forming a first waveguide positioned on a top side of the plane;
forming a first region laterally aligned with the first waveguide and having a first thermal conductivity;
forming a second waveguide positioned on the top side of the plane and laterally offset from the first waveguide; and
forming a second region laterally aligned with the second waveguide and having a second thermal conductivity different from the first thermal conductivity, wherein one of the first or second regions extends at least partially through the buried oxide layer toward the plane.