Radio frequency shielding within a semiconductor package
Radio frequency shielding within a semiconductor package is described. In one example, a multiple chip package has a digital chip, a radio frequency chip, and an isolation layer between the digital chip and the radio frequency chip. A cover encloses the digital chip and the radio frequency chip.
1. A multiple chip package comprising:
a first chip;
a second chip;
an isolation structure between the first chip and the second chip;
a first redistribution layer adjacent the first chip, wherein the first chip is connected to the first redistribution layer;
a molding compound partially enclosing first chip and the second chip;
wherein the first redistribution layer provides a connection between the first chip and a ball grid-array ball; and
wherein the first redistribution layer provides a connection between the second chip and a ball-grid array ball.
2. The package of claim 1 , wherein the isolation structure is formed over the first chip and adjacent to the first chip, and wherein the first chip is a digital first chip.
3. The package of claim 2 , wherein the isolation structure is a metallization layer.
4. The package of claim 3 , wherein the metallization layer is formed by chemical vapor deposition over the second chip.
5. The package of claim 3 , wherein the isolation structure is formed of copper.
6. The package of claim 1 , wherein the second chip is a radio frequency second chip.
7. The package of claim 1 , wherein the first chip and the second chip are stacked within the package.
8. The package of claim 1 , wherein the first chip is a processor and the and the second chip is a radio transceiver, the package further comprising a memory chip coupled to the processor and a radio frequency power amplifier coupled to the transceiver and wherein the isolation structure is between the processor and the memory chip on one side and between the radio transceiver and the power amplifier on the other side.
9. The package of claim 1 , further comprising a plurality of interconnects between the first chip and the second chip, wherein the interconnects bypass the isolation structure.
10. The package of claim 1 , further comprising a plurality of interconnects between the first chip and the second chip, where the interconnects pass through a respective plurality of cut openings in the isolation structure.
11. The package of claim 1 , further comprising a package substrate to which the molding compound is attached, the package substrate being directly attached to the first chip through a redistribution layer.
12. The package of claim 1 , further comprising a ground plane connection from the isolation structure to the substrate.