Integrated system of PDN implementation and digital co-synthesis

1. A method useful in integrated circuit design, comprising:

receiving, by a computer, design parameters for a power delivery network (PDN) to be instantiated in an integrated circuit chip (IC);

receiving, by the computer, a model of logic circuitry to be instantiated in the IC;

simulating, using the computer, operation of a plurality of configurations of the PDN based on the design parameters, for the model of logic circuitry over a specified range of minimum voltages to indicate a best-for-area PDN configuration and a best-for-power PDN configuration of the plurality of configurations of the PDN;

generating, using the computer, a netlist representation of a selected PDN configuration of the plurality of configurations of the PDN, the selected PDN configuration being the best-for-area PDN configuration or the best-for-power PDN configuration;

processing, using the computer, the netlist representation of the selected PDN configuration along with a digital circuit design for the logic circuitry to generate a combined digital circuit design of the selected PDN and logic circuitry; and

synthesizing, using the computer, the combined digital circuit design of the selected PDN and logic circuitry, for use in implementing the IC for the combined digital circuit design of the PDN and logic circuitry.

2. The method of claim 1 , wherein processing the netlist representation of the selected PDN configuration along with the digital circuit design for the logic circuitry further comprises adding the netlist representation of the selected PDN configuration into model libraries of a synthesis tool prior to synthesizing the netlist representation of the selected PDN configuration along with the digital circuit design for the logic circuitry.

3. The method of claim 1 , wherein processing the netlist representation of the selected PDN configuration along with the digital circuit design for the logic circuitry comprises placing of elements of the PDN configuration and the digital circuit design in a layout and determining routing of signals between the elements.

4. The method of claim 1 , wherein the parameters for the PDN comprise voltage regulator (VR) error, VR efficiency, and VR area.

5. The method of claim 4 , wherein the parameters for the PDN further comprise bump properties and on-die metal capacitor capacitance and area.

6. The method of claim 1 , wherein the model of logic circuitry comprises a model of area and current for the logic circuitry.

7. The method of claim 1 , wherein the netlist representation includes information regarding a number of bumps for the PDN.

8. The method of claim 1 , wherein the parameters for the PDN comprise automatic transient control (ATC) circuit area.

9. The method of claim 8 , wherein the netlist representation of the selected PDN configuration includes information regarding a number of embedded voltage regulators and a number of ATC circuits.