Fast pre-amp latch comparator

1. A high-speed comparator, comprising:

a differential amplifier configured to receive differential input signals and generate a differential pair of intermediate signals;

a latch configured to generate a pair of output signals at a respective pair of latching nodes based on the differential pair of intermediate signals;

a reset switch configured to control the pair of output signals based on a reset pulse so as to settle the pair of output signals, the reset switch configured to couple the pair of latching nodes; and

a pulse generator to generate the reset pulse;

wherein the differential amplifier comprises a first pull-up device and a first pull-down device connected in series, with a gate of the first pull-down device connected to a node between the first pull-up device and the first pull-down device, and a second pull-up device and a second pull-down device connected in series, with a gate of the second pull-down device connected to a node between the second pull-up device and the second pull-down device;

wherein the latch comprises a third pull-up device and a third pull-down device connected in series, and a fourth pull-up device and a fourth pull-down device connected in series, with gates and drains of the third and fourth pull-up devices cross-connected at the pair of latching nodes, and with gates of the third and fourth pull-down devices cross-connected with drains of the first and second pull-down devices at the node between the first pull-up device and the first pull-down device and the node between the second pull-up device and the second pull-down device;

wherein sources of the third and fourth pull-up devices are coupled to a power supply based on a clock signal; and

wherein the reset pulse has a duty cycle much smaller than the clock signal.

2. A method for operating a high-speed comparator having a differential amplifier and a latch comprising:

receiving a differential pair of input signals by the differential amplifier;

generating a differential pair of intermediate signals by the differential amplifier using the differential pair of input signals;

receiving, by the latch, the differential pair of intermediate signals, the latch driven by a clock signal;

providing, by the latch, a pair of output signals at a respective pair of latching nodes based on the differential pair of intermediate signals; and

activating a reset switch based on a reset pulse having a duty cycle, the reset switch coupling the pair of latching nodes, the duty cycle of the reset pulse being smaller than a duty cycle of the clock signal.

3. The method of claim 2 , further comprising:

generating the reset pulse for use in activating the reset switch based on an input signal and an intermediate signal provided by a variable delay block; and

stabilizing, by the reset switch, the pair of output signals when the reset switch is active.

4. The method of claim 2 , wherein the duty cycle of the reset pulse corresponds to a setup time for the latch.

5. The method of claim 2 , wherein the receiving the differential pair of input signals occurs at gates of p-channel transistors of the differential amplifier.

6. The method of claim 2 , wherein the receiving, by the latch, the differential pair of intermediate signals occurs at gates of n-channel transistors of the latch.

7. The method of claim 2 , further comprising activating a first output switch and activating a second output switch so as to stabilize the differential pair of intermediate signals.