Memory system capable of reliably processing data with reduced complexity and performance deterioration, and operating method thereof

1. A memory system comprising:

a memory device suitable for storing data; and

a controller suitable for programming test data to a first memory block of the memory device and programming meta-data corresponding to the programming of the test data to a second memory block of the memory device before a first time point when the memory system is changed from a power-on state to a power-off state at the first time point,

wherein when the memory system is changed to the power-on state at a second time point in a state where the memory system maintains the power-off state during a time period after the first time point, the controller reads the meta-data programmed in the second memory block at the second time point, and loads the read meta-data to a second buffer of the controller,

wherein the controller checks a first data distribution of the test data programmed before the first time point through the meta-data loaded in the second buffer, checks a second data distribution of the test data read out at the second time point through the read test data loaded in the first buffer,

wherein the controller checks a data offset of the test data through a difference between the first data distribution and the second data distribution, adjusts a parameter of the memory system by as much as the data offset of the test data, and performs a command operation to the memory system using the adjusted parameter, and

wherein the parameter includes a number or locations of memory cells.

2. The memory system of claim 1 , wherein the controller generates the test data with a predetermined pattern, stores the generated test data in a first buffer, and programs the test data stored in the first buffer to the first memory block before the first time point, and

wherein the controller generates the meta-data according to the program of the test data, stores the generated meta-data in the second buffer, and programs the meta-data stored in the second buffer to the second memory block before the first time point.

3. The memory system of claim 2 , wherein the controller checks map data of the test data through the meta-data loaded in the second buffer, reads the test data programmed in the first memory block through the map data, and loads the read test data to the first buffer.

4. The memory system of claim 1 , wherein the controller checks a voltage distribution of memory cells storing the test data programmed before the first time point and a voltage distribution of the memory cells storing the test data read out at the second time point as the first data distribution and the second data distribution of the test data, respectively.

5. The memory system of claim 1 , wherein the controller checks a number of memory cells or locations of memory cells storing the test data programmed before the first time point and the number or locations of the memory cells storing the test data read out at the second time point as the first data distribution and the second data distribution, respectively.

6. The memory system of claim 1 , wherein the controller programs the test data to all pages included in the first memory block or a first page among all the pages.

7. The memory system of claim 6 , wherein the meta-data comprises a number of memory cells or locations of memory cells in which the test data are programmed, among a plurality of memory cells included in all the pages or the first page.

8. An operating method of a memory system including a memory device, comprising:

confirming that the memory device is changed to a power-off state from a power-on state at a first time point;

programming test data to a first memory block of the memory device before the first time point;

programming meta-data corresponding to the programming of the test data to a second memory block of the memory device before the first time point,

confirming that the memory system is changed to the power-on state at a second time point, in a state where the memory system maintains the power-off state during a time period after the first time point;

reading the meta data programmed in the second memory block at the second time point, and loading the read meta data to a second buffer;

checking a first data distribution of the test data programmed before the first time point through the meta-data loaded in the second buffer;

checking a second data distribution of the test data read out at the second time point through the read test data loaded in the first buffer;

checking a data offset of the test data through difference between the first data distribution and the second data distribution;

adjusting a parameter of the memory system by as much as the data offset of the test data, wherein the parameter of the memory system includes a number or locations of memory cells; and

performing a command operation to the memory system using the adjusted parameter.

9. The operating method of claim 8 ,

wherein the programming of the test data to the first memory block before the first time point comprises:

generating the test data with a predetermined pattern and storing the generated test data in a first buffer; and

programming the test data stored in the first buffer to the first memory block, and

wherein the programming of the meta-data to the second memory block before the first time point comprises:

generating the meta-data and storing the generated meta-data in the second buffer; and

programming the meta-data stored in the second buffer to the second memory block.

10. The operating method of claim 9 , further comprising:

checking map data of the test data through the meta-data loaded in the second buffer; and

reading the test data programmed in the first memory block through the map data, and loading the read test data to the first buffer.

11. The operating method of claim 8 , wherein the checking of the first data distribution and the second data distribution comprises checking a voltage distribution of memory cells storing the test data programmed before the first time point and a voltage distribution of the memory cells storing the test data read out at the second time point as the first data distribution and the second data distribution of the test data, respectively.

12. The operating method of claim 8 , wherein the checking of the first data distribution and the second data distribution comprises checking a number of memory cells or locations of memory cells storing the test data programmed before the first time point and the number or locations of the memory cells storing the test data read out at the second time point as the first data distribution and the second data distribution, respectively.

13. The operating method of claim 8 , wherein the programming of the test data to the first memory block comprises programming the test data to all pages included in the first memory block or a first page among all the pages.

14. The operating method of claim 13 , wherein the meta-data comprises a number of memory cells or locations of memory cells in which the test data are programmed, among a plurality of memory cells included in all the pages or the first page.