Jitter improvement in serializer-deserializer (SerDes) transmitters
Systems and methods are provided for jitter improvement in serializer-deserializer (SerDes) transmitters. One or more adjustments may be applied in SerDes transmitter circuitry to reduce jitter in a serial output of the SerDes transmitter circuitry, which may occur as a result of processing of input data. Applying the one or more adjustments may comprise use of dummy data. The dummy data may be configured to generate corresponding dummy current pulses which may in turn be used in controlling supply variations occurring during processing of the input data and/or generation of the serial output. The dummy data may be configured to generate the dummy current pulses such that they are applied along with current pulses corresponding to the input data. The dummy data may be adaptively set or adjusted based on the input data. The use of the dummy data may be selectively turned on or off.
1. A system comprising:
a pulse generation circuit configured for generating programmable and adjustable dummy current pulses for use in serializer/deserializer (SerDes) transmitters, wherein the pulse generation circuit comprises:
one or more dummy load cells, wherein each dummy load cell is configurable to program load and complementary dummy current spikes; and
one or more control elements for controlling the one or more dummy load cells based on one or more input signals to the pulse generation circuit;
wherein:
the generated dummy current pulses are configurable for use in controlling supply variations during processing of input data for serializer/deserializer (SerDes) transmission;
the one or more control elements are arranged to control generation of dummy current pulses via the one or more dummy load cells based on the one or more input signals; and
the one or more input signals comprise at least one signal corresponding to the input data.
2. The system of claim 1 , wherein the one or more control elements comprise one or more of n-channel transistors and p-channel transistors.
3. The system of claim 1 , wherein the one or more control elements comprise one or more inverters.
4. The system of claim 1 , wherein the pulse generation circuit is configured to generate the dummy current pulses to eliminate or reduce supply variations during processing of the input data.