Microfabricated ultrasonic transducers and related apparatus and methods
Micromachined ultrasonic transducers integrated with complementary metal oxide semiconductor (CMOS) substrates are described, as well as methods of fabricating such devices. Fabrication may involve two separate wafer bonding steps. Wafer bonding may be used to fabricate sealed cavities in a substrate. Wafer bonding may also be used to bond the substrate to another substrate, such as a CMOS wafer. At least the second wafer bonding may be performed at a low temperature.
1. A method of forming an ultrasound-on-a-chip device including an integrated complementary metal oxide semiconductor (CMOS) circuit, the method comprising:
forming a cavity in a first wafer, wherein the first wafer comprises a silicon-on-insulator (SOI) wafer;
forming a composite substrate by fusion bonding a second wafer with the first wafer so as to seal the cavity, and annealing the composite substrate, wherein the second wafer comprises a silicon-on-insulator (SOI) wafer, and wherein forming the composite substrate comprises bonding a silicon device layer of the second wafer with an oxide layer formed on a first side of a silicon device layer of the first wafer, the cavity being formed in the oxide layer;
forming a conductive contact on an electrode region of the composite substrate;
removing a handle layer and a buried oxide (BOX) layer of the first wafer prior to bonding the composite substrate to a third wafer having the integrated CMOS circuit formed therein;
bonding the composite substrate to the third wafer having the integrated CMOS circuit formed therein, using the conductive contact; and
thinning the composite substrate to form a flexible membrane proximate the cavity.
2. The method of claim 1 , wherein the fusion bonding is performed in vacuum at a temperature below 450° C.
3. The method of claim 2 , wherein the sealed cavity has a pressure from about 1×10 −3 Torr to about 1×10 −5 Torr.
4. The method of claim 1 , wherein the annealing is performed at a temperature between approximately 500° C. and approximately 1500° C.
5. The method of claim 1 , wherein the bonding the composite substrate to the third wafer comprises forming one of: a thermocompression bond, a eutectic bond, or a silicide bond at a temperature below 450° C.
6. The method of claim 1 , further comprising forming an isolation trench in a second side of the silicon device layer of the first wafer, the isolation trench corresponding to a location of the cavity.
7. The method of claim 1 , wherein the cavity comprises a portion of an ultrasonic transducer.
8. An ultrasound-on-a-chip device, comprising:
a composite, capacitive micromachined ultrasonic transducer (CMUT) substrate, comprising a first wafer having an ultrasonic transducer cavity and a second wafer bonded to the first wafer, defining an oxide-to-oxide bond that seals the ultrasonic transducer cavity, wherein the ultrasonic transducer cavity is at a pressure from about 1×10 −3 Torr to about 1×10 −5 Torr;
a conductive contact disposed on an electrode region of the composite CMUT substrate;
a third wafer having an integrated circuit formed therein, the third wafer bonded to the composite CMUT substrate using the conductive contact, wherein:
the composite CMUT substrate has a thinned surface to form a flexible membrane proximate the ultrasonic transducer cavity;
the ultrasonic transducer cavity is formed in a first thermal oxide layer of the first wafer;
the second wafer has a second thermal oxide layer such that the composite CMUT substrate comprises an oxide-to-oxide bond that seals the ultrasonic transducer cavity;
the second wafer includes a thinned bulk silicon layer that comprises a bottom electrode for the ultrasonic transducer cavity; and
the first wafer includes a silicon device layer that comprises the flexible membrane proximate the ultrasonic transducer cavity; and
an isolation structure formed in the bottom electrode so as to electrically isolate a section of the bottom electrode corresponding to the ultrasonic transducer cavity, wherein the isolation structure extends through the thinned bulk silicon layer comprising the bottom electrode.
9. The ultrasound-on-a-chip device of claim 8 , wherein the isolation structure comprises a trench within the thinned bulk silicon layer that is filled with an insulating layer.
10. The ultrasound-on-a-chip device of claim 8 , wherein the bottom electrode comprises doped sections of the thinned bulk silicon layer and the isolation structure comprises an undoped section of the thinned bulk silicon layer.