Pre-Emphasis and Equalization for DRAM
The present disclosure is directed to apparatuses and methods to pre-compensate and/or post-compensate for inter-symbol interference (ISI). The apparatuses and methods of the present disclosure can be implemented as part of an I/O interface in a memory or memory controller, including dynamic random access memory (DRAM).
1 . An apparatus, comprising:
a data bus; and
an input/output (IO) interface, implemented within a dynamic random-access memory (DRAM) or memory controller, configured to receive the data over a data bus,
wherein the I/O interface comprises an intersymbol interference (ISI) post-compensation circuit configured to add an ISI compensation factor, determined based on a first bit of the data received over the data bus, to a reference voltage used to determine a logic value of a second bit received over the data bus immediately following the first bit of data.
2 . The apparatus of claim 1 , further comprising:
a dynamic random-access memory (DRAM) subarray for storing data; and
a row buffer configured to write the data to the DRAM subarray,
wherein the I/O interface is configured to receive the data over the data bus from a memory controller.
3 . The apparatus of claim 1 , wherein the I/O interface is implemented in the memory controller and is configured to receive the data over the data bus from the DRAM.
4 . The apparatus of claim 1 , wherein the I/O interface is implemented in accordance with a low-power double date rate (LPDDR) RAM interface specification.
5 . The apparatus of claim 1 , wherein each line of the data bus is coupled to a different instance of the ISI post-compensation circuit.
6 . The apparatus of claim 1 , wherein the ISI post-compensation circuit includes two parallel paths, each configured to add a different value of the ISI compensation factor to the reference voltage.
7 . A dynamic random-access memory (DRAM), comprising:
a DRAM subarray for storing data;
a row buffer configured to read the data from the DRAM subarray; and
an input/output (I/O) interface, configured to transmit the data over a data bus to a memory controller, comprising an intersymbol interference (ISI) pre-compensation circuit configured to pre-emphasize the data before the data is transmitted over the data bus to the memory controller, wherein the ISI pre-compensation circuit comprises:
a first flip-flop comprising a first flip-flop input and a first flip-flop output, wherein the first flip-flop input is configured to receive the data from the DRAM subarray;
a second flip-flop comprising a second flip-flop input and a second flip-flop output, wherein the second flip-flop input is coupled to the first flip-flop output;
a sourcing driver multiplexer (MUX) configured to provide a sourcing driver control signal based on the first flip-flop output and the second flip-flop output;
a sinking driver MUX configured to provide a sinking driver control signal based on the second flip-flop output;
a sourcing driver configured to provide a sourcing drive signal with a drive strength determined based on the sourcing driver control signal; and
a sinking driver configured to provide a sinking drive signal with a drive strength determined based on the sinking driver control signal.
8 . The DRAM of claim 7 , Wherein the ISI pre-compensation circuit is configured to combine the sourcing drive signal and the sinking drive signal.
9 . The DRAM of claim 7 , wherein the I/O interface is implemented in accordance with a low-power double date rate (LPDDR) RAM interface specification.
10 . The DRAM of claim 7 , wherein each line of the data bus is coupled to a different instance of the ISI pre-compensation circuit.
11 . The DRAM of claim 7 , wherein the ISI pre-compensation circuit is configured to pre-emphasize a logic “1” that follows a logic “0” in the data before the data is transmitted over the data bus to the memory controller by driving the logic “1” on the data bus to a higher voltage than a voltage level corresponding to logic “1” values.
12 . The DRAM of claim 7 , wherein the ISI pre-compensation circuit is configured to pre-emphasize a logic “0” that follows a logic “1” in the data before the data is transmitted over the data bus to the memory controller by driving the logic “0” on the data bus to a lower voltage than a voltage level corresponding to logic “0” values.
13 . The DRAM of claim 7 , wherein the sourcing driver MUX is configured to couple one of four different input control signal Values to the sourcing driver based on the first flip-flop output and the second flip-flop output.
14 . An intersymbol interference (ISI) pre-compensation circuit for pre-emphasizing data before the data is transmitted over a data bus, comprising:
a first flip-flop comprising a first flip-flop input and a first flip-flop output, wherein the first flip-flop input is configured to receive the data;
a second flip-flop comprising a second flip-flop input and a second flip-flop output, wherein the second flip-flop input is coupled to the first flip-flop output;
a sourcing driver multiplexer (MUX) configured to provide a sourcing driver control signal based on the first flip-flop output and the second flip-flop output;
a sinking driver MUX configured to provide a sinking driver control signal based on the second flip-flop output;
a sourcing driver configured to provide a sourcing drive signal with a drive strength determined based on the sourcing driver control signal; and
a sinking driver configured to provide a sinking drive signal with a drive strength determined based on the sinking driver control signal.
15 . The ISI pre-compensation circuit of claim 14 , wherein the sourcing drive signal and the sinking drive signal are combined to generate pre-emphasized data.
16 . The ISI pre-compensation circuit of claim 15 , wherein:
a logic “1” that follows a logic “0” in the data is driven to a higher voltage than a voltage level corresponding to logic “1” values in the pre-emphasized data; and
a logic “0” that follows a logic “1” in the data is driven to a lower voltage than a voltage level corresponding to logic “0” values in the pre-emphasized data.
17 . The ISI pre-compensation circuit of claim 14 , wherein the ISI pre-compensation circuit is implemented in an input/output (I/O) interface.
18 . The ISI pre-compensation circuit of claim 14 , wherein the I/O interface is implemented in accordance with a low-power double date rate (LPDDR) RAM interface specification.
19 . The ISI pre-compensation circuit of claim 14 , wherein ISI pre-compensation circuit is implemented in a memory controller.
20 . The ISI pre-compensation circuit of claim 14 , wherein ISI pre-compensation circuit is implemented in a dynamic random access memory (DRAM).