IP Library Granted Patent US 9,666,290
Granted Patent B2
US 9,666,290 · App. 15/182,411 · Granted May 30, 2017

Flash memory counter

Inventors: Ronny Van Keer (Hoeilaart, BE); Youssef Ahssini (Vilvoorde, BE)
Assignee: Proton World International N.V.
G11C16/14G06F12/0246G11C16/20G11C16/26G11C16/345
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Quick Facts
Patent No.
US 9,666,290
App. No.
15/182,411
Granted
May 30, 2017
Kind
B2
Abstract

A method of updating a counter in a flash memory includes a first phase where a set of values capable of being taken by the counter are programmed in at least one page of the flash memory. A second phase of updating the counter programs a state zero in the flash memory each time the counter is incremented/decremented.

Claims (36)

1. A method of operating a counter, comprising:

after programming a first value into a first location of a block of memory, programming a next progressive value into each subsequent location of the block of memory, each next progressive value being a next progressively different value than its predecessor; and

incrementing the counter by interrogating locations in the block of memory until a location having one of the next progressively different values is identified and programming a clearing value into the identified location having the one of the next progressively values.

2. A method of operating a counter according to claim 1 , wherein the block of memory is in a flash memory.

3. A method of operating a counter according to claim 1 , wherein the block of memory has 64 locations, 128 locations, or 256 locations.

4. A method of operating a counter according to claim 1 , wherein the counter rolls over after every location in the block of memory has the clearing value.

5. A method of operating a counter according to claim 1 , wherein each next progressive value is one more or one less than its predecessor.

6. A method of operating a counter according to claim 1 , comprising:

erasing at least one page of the block of memory.

7. An electronic device, comprising:

a memory having a plurality of storage locations allocated to a counter including a first counter location, a last counter location and a plurality of counter locations between the first counter location and the last counter location; and

a counter circuit, the counter circuit arranged to initialize each of the plurality of storage locations to a different initialization value and the counter circuit arranged to increment the counter, the incrementing including:

beginning with the first counter location and working toward the last counter location, identifying a next counter location having one of the different initialization values; and

programming a clearing value into the identified next counter location.

8. An electronic device according to claim 7 , wherein the memory is a flash memory in a wireless transceiver circuit.

9. An electronic device according to claim 8 , wherein the wireless transceiver circuit conforms to a near field communications (NFC) protocol.

10. An electronic device according to claim 7 , wherein the counter circuit is arranged to pre-initialize the plurality of storage locations by erasing at least one page of the memory.

11. An electronic device according to claim 7 , wherein the counter is arranged to count from 0 to 255 or wherein the counter is arranged to count from 255 to 0.

12. An electronic device according to claim 7 , wherein the plurality of storage locations allocated to the counter comprise N storage locations, N being an integer raised to a power of two.

13. A method to update a counter in a memory, comprising:

allocating N locations in the memory for the counter, each of the N locations representing a different sequential count value that the counter may take, the N locations beginning with a first location and ending with a last location;

initializing each of the N locations to a different initialized value; and

incrementing the counter, the incrementing including:

until a location having an initialized value is found, sequentially reading ones of the N locations in the memory from the first location toward the last location; and

programming a clearing value into the location having the initialized value that was found.

14. A method to update a counter in a memory according to claim 13 , comprising:

reading the counter, the reading including sequentially reading ones of the N locations in the memory from the first location toward the last location until a location having one of the initialized values is found; and

returning the one of the initialized values that was found.

15. A method to update a counter in a memory according to claim 13 , comprising:

reading the counter, the reading including identifying a first occurrence of a memory location having one of the initialized values; and

returning a value associated with the first occurrence of the memory location.

16. A method to update a counter in a memory according to claim 13 , wherein the counter is arranged with N−2 locations between the first location and the last location.

17. A method to update a counter in a memory according to claim 13 , wherein each of the N locations in the memory between the first location and the last location occupies a next sequential address of the memory.

18. A method to update a counter in a memory according to claim 13 , wherein the counter is a count-down counter and each increment of the counter programs the clearing value into a sequentially lower address of the memory.

19. A method to update a counter in a memory according to claim 13 , wherein the clearing value is not zero.

20. A method to update a counter in a memory according to claim 13 , wherein initializing each of the N locations includes erasing at least one page of the memory.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 16, 2022
From: PROTON WORLD INTERNATIONAL N.V.
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 061796/0130 →
Priority Claims (1)
FR 13 60440 · Oct 25, 2013 · national
Continuity (2)
Continuation 14522007 · Oct 23, 2014
Related Publication 20160293262A1 · Oct 6, 2016