IP Library Granted Patent US 9,653,324
Granted Patent B2
US 9,653,324 · App. 15/182,434 · Granted May 16, 2017

Integrated circuit package configurations to reduce stiffness

Inventors: Sven Albers (Regensburg, DE); Sonja Koller (Regensburg, DE); Thorsten Meyer (Regensburg, DE); Georg Seidemann (Landshut, DE); Christian Geissler (Teugn, DE); Andreas Wolter (Regensburg, DE)
Assignee: INTEL IP CORPORATION
H01L21/56H01L21/78H01L23/3128H01L23/562H01L24/97H01L2924/12042H01L2924/15311H01L2924/181H01L2924/1815H01L2924/3511
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Quick Facts
Patent No.
US 9,653,324
App. No.
15/182,434
Granted
May 16, 2017
Kind
B2
Abstract

Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed.

Claims (10)

1. A method of assembling an integrated circuit package comprising:

providing a die having a first side and a second side disposed opposite to the first side;

depositing an encapsulation material to encapsulate one or more surfaces of the die in the encapsulation material, the encapsulation material forming a first surface that is adjacent to the first side of the die and a second surface, opposite the first surface; and

shaping the second surface of the encapsulation material to include one or more trenches that have a length as measured in a plane parallel to the second surface that is greater than a width that is measured in a plane parallel to the second surface and perpendicular to the length such that the encapsulation material varies in thickness resulting in one or more areas of a cross-section of the integrated circuit package as measured at a trench is thinner than one or more other areas of the cross-section as measured at a portion of the integrated circuit package that does not intersect with a trench.

2. The method of claim 1 , wherein shaping the second surface of the encapsulation material comprises stamping the second surface of the encapsulation material to cause the encapsulation material to vary in thickness.

3. The method of claim 1 , wherein shaping the second surface of the encapsulation material comprises selectively removing encapsulation material from the second surface of the encapsulation material to cause the encapsulation material to vary in thickness.

4. The method of claim 1 , wherein shaping the second surface of the encapsulation material comprises shaping a portion of the second surface disposed external to a region over the die that is defined by a peripheral edge of the die.

5. The method of claim 4 , wherein shaping a portion of the second surface is selected from a group consisting of beveling of an edge or chamfering of an edge of the portion of the second surface.

6. The method of claim 4 , wherein shaping a portion of the second surface comprises forming one or more steps in the portion of the second surface.

7. The method of claim 1 , wherein the one or more trenches include at least four trenches that form a perimeter around the die.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 8, 2021
From: INTEL IP CORPORATION
To: INTEL CORPORATION
Reel/Frame 056524/0373 →
Continuity (2)
Division 14189938 · Feb 25, 2014
Related Publication 20160293453A1 · Oct 6, 2016