NON-VOLATILE DOUBLE SCHOTTKY BARRIER MEMORY CELL
A three terminal ReRAM device, which combines a Schottky barrier transistor and a Schottky barrier ReRAM into a single device is provided. The Schottky transistor memory device includes a source region, a drain region, and a gate electrode. Between the source and drain regions, the ReRAM material is present. The ReRAM material can include a metal oxide, such as zinc or hafnium oxide. A Schottky barrier forms naturally between the drain region and the ReRAM material. As voltage is applied to the gate electrode and the source region, the Schottky barrier breaks down, leading to the formation of a filament across the drain region and the ReRAM material. The filament is non-volatile and short-circuits the reverse-biased barrier, keeping the device in a low resistance state. The filament can be removed by reversing the polarity of the voltage such that the device switches back to a high resistance state.
1 . A memory device, comprising:
an insulating layer;
a source region disposed on the insulating layer;
a drain region disposed on the insulating layer;
a ReRAM material layer disposed on the insulating layer in between the source region and the drain region; and
a gate electrode disposed over the ReRAM material layer.
2 . The device of claim 1 , wherein the ReRAM material layer comprises a metal oxide material.
3 . The device of claim 2 , wherein the metal oxide material comprises a material selected from the group consisting of zinc oxide, hafnium oxide, tantalum oxide, titanium oxide, vanadium oxide, tungsten oxide, zirconium oxide, nickel oxide, copper oxide and combinations thereof.
4 . The device of claim 1 , wherein the ReRAM material layer comprises a metal oxide having a first oxidation state, the drain region comprises the same metal oxide having a second oxidation state different that the first oxidation state.
5 . The device of claim 1 , wherein ReRAM material layer comprises doped metal oxide.
6 . The device of claim 1 , wherein ReRAM material layer comprises a metal oxide having a first composition and the drain region comprises a metal oxide having a second composition different than the first composition.
7 . The device of claim 1 , wherein the ReRAM material layer comprises a metal oxide and the drain region comprises a metal.
8 . The device of claim 1 , wherein the gate electrode is disposed on the ReRAM material layer and a Schottky barrier is present between the gate electrode and the ReRAM material layer.
9 . The device of claim 1 , wherein a resistive or dielectric layer having a resistance greater than a resistance of the gate electrode is disposed between the gate electrode and the ReRAM material layer.
10 . The device of claim 9 , wherein the resistive layer comprises a material selected from the group consisting of TaN, RuO 2 , PbO, Bi 2 Ru 2 O 7 , NiCr, and combinations thereof.
11 . A memory device, comprising:
an insulating layer;
a source region disposed on the insulating layer;
a drain region disposed on the insulating layer;
a ReRAM material layer disposed on the insulating layer between the source region and the drain region;
a gate electrode disposed over the ReRAM material layer; and
a conductive anodic filament extending from the drain region to the ReRAM material layer.
12 . The device of claim 11 , wherein the ReRAM material layer comprises a metal oxide material.
13 . The device of claim 12 , wherein the metal oxide material comprises a material selected from the group consisting of zinc oxide, hafnium oxide, tantalum oxide, titanium oxide, vanadium oxide, tungsten oxide, zirconium oxide, nickel oxide, copper oxide, PCMO and combinations thereof.
14 . The device of claim 11 , wherein the ReRAM material layer comprises a metal oxide having a first oxidation state, the drain region comprises the same metal oxide having a second oxidation state different that the first oxidation state.
15 . The device of claim 11 , wherein ReRAM material layer comprises doped metal oxide.
16 . The device of claim 11 , wherein ReRAM material layer comprises a metal oxide having a first composition and the drain region comprises a metal oxide having a second composition different than the first composition.
17 . The device of claim 11 , wherein the ReRAM material layer comprises a metal oxide and the drain region comprises a metal.
18 . The device of claim 11 , wherein the gate electrode is disposed on the ReRAM material layer and a Schottky barrier is present between the gate electrode and the ReRAM material layer.
19 . The device of claim 11 , wherein a resistive layer having a resistance greater than a resistance of the gate electrode is disposed between the gate electrode and the ReRAM material layer.
20 . The device of claim 19 , wherein the resistive layer comprises a material selected from the group consisting of TaN, RuO 2 , PbO, Bi 2 Ru 2 O 7 , NiCr, and combinations thereof.
21 . A memory array comprising one or more memory devices, at least one of the devices comprising:
an insulating layer;
a source region disposed on the insulating layer;
a drain region disposed on the insulating layer;
a ReRAM material layer disposed on the insulating layer in between the source region and the drain region;
a gate electrode disposed over the ReRAM material layer; and
a conductive anodic filament extending from the drain region to the ReRAM material layer.
22 . The memory array of claim 21 , wherein the ReRAM material layer comprises a metal oxide material.
23 . The memory array of claim 22 , wherein the metal oxide material comprises a material selected from the group consisting of zinc oxide, hafnium oxide, tantalum oxide, titanium oxide, vanadium oxide, tungsten oxide, zirconium oxide, nickel oxide, copper oxide and combinations thereof.
24 . The memory array of claim 21 , wherein the ReRAM material layer comprises a metal oxide having a first oxidation state, the drain region comprises the same metal oxide having a second oxidation state different that the first oxidation state.
25 . The memory array of claim 21 , wherein ReRAM material layer comprises doped metal oxide.
26 . The memory array of claim 21 , wherein ReRAM material layer comprises a metal oxide having a first composition and the drain region comprises a metal oxide having a second composition different than the first composition.
27 . The memory array of claim 21 , wherein the ReRAM material layer comprises a metal oxide and the drain region comprises a metal.
28 . The memory array of claim 21 , wherein the gate electrode is disposed on the ReRAM material layer and a Schottky barrier is present between the gate electrode and the ReRAM material layer.
29 . The memory array of claim 21 , wherein a resistive layer having a resistance greater than a resistance of the gate electrode is disposed between the gate electrode and the ReRAM material layer.
30 . The memory array of claim 29 , wherein the resistive layer comprises a material selected from the group consisting of TaN, RuO 2 , PbO, Bi 2 Ru 2 O 7 , NiCr, and combinations thereof.