Duty-cycled high speed clock and data recovery with forward error correction assist
A method and system for duty-cycled high speed clock and data recovery with forward error correction are provided. The system operates on a first digital signal comprising a first plurality of samples and a second digital signal comprising a second plurality of samples. The second plurality of samples may be a subset of the first plurality of samples, for example, if the first and second pluralities of samples are generated by one analog-to-digital converter. A clock and data recovery module is operable to produce a timing indication according the second digital signal. The second plurality of samples is sampled intermittently. The discontinuity between bursts of samples in the second signal corresponds to a duty cycle. A forward error correction module is operable to produce a digital error-corrected signal according to the first digital signal and the timing indication.
1. A receiver for data communications, comprising:
a forward error correction circuit operable to produce a digital error-corrected signal according to a first digital signal and a timing indication, the first digital signal comprising a first plurality of samples, the first plurality of samples being sampled continuously by a first clock having a first sample rate and a first phase; and
a clock and data recovery circuit operable to increase an accuracy of the timing indication according a second digital signal, wherein:
the second digital signal comprises a second plurality of samples,
the second plurality of samples comprises bursts of two or more samples spanning a first length of time,
the two or more samples in a burst are sampled by a second clock having a second sample rate and a second phase, and
a ratio between a burst length and a discontinuity between consecutive bursts of two or more samples corresponds to a duty cycle of a third clock that is slower than the second sample rate.
2. The receiver of claim 1 , wherein the second plurality of samples is a subset of the first plurality of samples.
3. The receiver of claim 1 , wherein the second plurality of samples is produced by a high-speed, high-bandwidth photodiode that intermittently monitors an optical signal.
4. The receiver of claim 1 , wherein the forward error correction module is operably connected to a continuous time linear equalizer.
5. The receiver of claim 1 , wherein the first sample rate is equal to a symbol rate of received data.
6. The receiver of claim 1 , wherein the second sample rate is equal to twice a symbol rate of received data.
7. The receiver of claim 1 , wherein the duty cycle is one percent or less.
8. The receiver of claim 1 , wherein the second clock is out of phase with the first clock.
9. A method for receiving data, comprising:
continuously sampling an analog signal at a first sample rate, using a clock and data recovery circuit, to produce a first plurality of samples;
sampling the analog signal in bursts of two or more samples, using the clock and data recovery circuit, to produce a second plurality of samples, wherein samples within a burst are at a second sample rate, and wherein a ratio between a burst length and a discontinuity between consecutive bursts corresponds to a duty cycle of a clock that is slower than the second sample rate;
recovering a timing indication, with increased accuracy, according to the second plurality of samples; and
producing, using a forward error correction circuit, a digital error-corrected signal according to the first plurality of samples and the timing indication.
10. The method of claim 9 , wherein the second plurality of samples is a subset of the first plurality of samples.
11. The method of claim 9 , wherein the second plurality of samples is produced by a high-speed, high-bandwidth photodiode that intermittently monitors an optical signal.
12. The method of claim 9 , wherein the method comprises equalizing the first plurality of samples.
13. The method of claim 9 , wherein the first sample rate is equal to a symbol rate of received data.
14. The method of claim 9 , wherein the second sample rate is equal to twice a symbol rate of received data.
15. The method of claim 9 , wherein the duty cycle is one percent or less.
16. The method of claim 9 , wherein the second sample rate is out of phase with the first sample rate.
17. A machine-readable storage having stored thereon, a computer program having at least one code section for enabling data reception, the at least one code section being executable by a machine for causing the machine to perform operations comprising:
continuously sampling an analog signal at a first sample rate, using a clock and data recovery circuit, to produce a first plurality of samples;
sampling the analog signal in bursts of two or more samples, using the clock and data recovery circuit, to produce a second plurality of samples, wherein samples within a burst are at a second sample rate, and wherein a ratio between a burst length and a discontinuity between consecutive bursts corresponds to a duty cycle of a clock that is slower than the second sample rate;
recovering a timing indication, with increased accuracy, according to the second plurality of samples; and
producing, using a forward error correction circuit, a digital error-corrected signal according to the first plurality of samples and the timing indication.
18. The machine-readable storage of claim 17 , wherein the second plurality of samples is a subset of the first plurality of samples.
19. The machine-readable storage of claim 17 , wherein the duty cycle is one percent or less.
20. The machine-readable storage of claim 17 , wherein the second sample rate is out of phase with the first sample rate.