FORMING AIR GAP
A method of forming an air gap for a semiconductor device and the device formed are disclosed. The method may include forming conductive interconnects in an ILD including a high etch selectivity dielectric layer such as a silicon nitride with hydrogen component (SiNH) layer, and patterning an air gap mask layer preferably using extreme ultraviolet (EUV) light form an air gap mask. The air gap mask may be used to etch an air gap space in the high etch selectivity dielectric layer. Use of EUV with the high etch selectivity dielectric layer provides an air gap having a width of no greater than 15 nm with the opening used to form the air gap space having a width of no greater than 10 nm width. This integration approach offers smaller pinch-off height, e.g., less than approximately 6 nm, which improves process window for subsequent Mx+1 module builds.
1 - 11 . (canceled)
12 . A semiconductor device, comprising:
an interconnect layer over a device layer, wherein the interconnect layer includes:
a first low dielectric constant (low-K) dielectric layer under a high etch selectivity dielectric layer, and
a pair of immediately adjacent conductive interconnects; and
a plurality of air gaps located between the pair of immediately adjacent conductive interconnects.
13 . The semiconductor device of claim 12 , further comprising a cap layer over the low-K dielectric interconnect layer, the cap layer including a plurality of openings forming part of the plurality of air gaps in the low-K dielectric layer.
14 . The semiconductor device of claim 12 , further comprising a second low-K dielectric layer sealing the plurality of openings of the plurality of air gaps.
15 . The semiconductor device of claim 14 , wherein a pinch-off height of the second low-K dielectric layer is less than approximately 6 nm.
16 . The semiconductor device of claim 12 , wherein each conductive interconnect includes a wire, and at least 50% of a height of the wire is within the high etch selectivity dielectric layer.
17 . The semiconductor device of claim 12 , wherein the high etch selectivity dielectric layer includes silicon nitride with hydrogen component (SiNH) layer over the first low-K dielectric layer.
18 . The semiconductor device of claim 12 , wherein each air gap has a width of no greater than approximately 15 nm between the pair of conductive interconnects.
19 . The semiconductor device of claim 12 , wherein the plurality of air gaps have a spacing equal to a width thereof between the pair of conductive interconnects.
20 . A semiconductor device, comprising:
a plurality of interconnect layers over a device layer, each interconnect layer including a pair of immediately adjacent conductive interconnects each having a width less than approximately 10 nanometers (nm); and
a plurality of air gaps in at least one of the plurality of interconnect layers, the plurality of air gaps located between the pair of immediately adjacent conductive interconnects, wherein each of the plurality of air gaps has a width no greater than approximately 15 nm in a direction perpendicular to the at least one conductive interconnect.
21 . The semiconductor device of claim 12 , wherein each of the plurality of air gaps has a width no greater than approximately 15 nm perpendicular to the pair of conductive interconnects.
22 . The semiconductor device of claim 13 , wherein each of the plurality of openings has a width no greater than approximately 10 nm perpendicular to the pair of conductive interconnects.
23 . The semiconductor device of claim 13 , wherein each of the plurality of openings has a width of approximately 5 nm perpendicular to the pair of conductive interconnects.
24 . The semiconductor device of claim 13 , further comprising an air gap capping layer over the cap layer, wherein the air gap capping layer seals the plurality of openings of each of the plurality of air gaps.
25 . The semiconductor device of claim 24 , wherein each of the plurality of air gaps includes a pinch-off height that extends above the cap layer into the air gap capping layer.
26 . The semiconductor device of claim 25 , wherein the pinch-off height is no greater than approximately 20% of the air gap capping layer.