Array substrate and fabrication method, display panel, and display device

1. An array substrate, comprising: a substrate; a first functional layer configured on one side of the substrate; a first insulating layer configured on the first functional layer facing away from the substrate; a second functional layer configured on the first insulating layer facing away from the substrate; a second insulating layer configured on the second functional layer facing away from the substrate; a third functional layer configured on the second insulating layer facing away from the substrate; a third insulating layer configured on the third functional layer facing away from the substrate; a fourth functional layer configured on the third insulating layer facing away from the substrate; a plurality of through-holes configured to electrically connect different functional layers, wherein a depth of any through-holes does not exceed the thickness of two adjacent insulating layers; and a plurality of pixel driving circuits, wherein a pixel driving circuit comprises a first transistor, wherein a semiconductor layer of the first transistor is located in the first functional layer, a gate electrode of the first transistor is located in the second functional layer, and a source electrode and a drain electrode of the first transistor are both located in the fourth functional layer.

2. The array substrate of claim 1 , wherein:

the functional layers and the insulating layers are single layer structures or multi-layer structures including a plurality of sub-layers.

3. The array substrate of claim 1 , wherein:

the first functional layer is made of semiconductor material; and

the second functional layer, the third functional layer, and the fourth functional layer are made of metal.

4. The array substrate of claim 1 , wherein:

orthogonal projection centers of any two through-holes on the substrate do not coincide with each other.

5. The array substrate of claim 1 , wherein:

the first insulating layer has a thickness of approximately 100 nm to 200 nm;

the second insulating layer has a thickness of approximately 50 nm to 150 nm; and

the third insulating layer has a thickness of approximately 200 nm to 700 nm.

6. The array substrate of claim 1 , wherein:

the third functional layer includes a first conductive portion and a second conductive portion;

the through-holes include a first through-hole and a second through-hole that penetrate the first insulating layer and the second insulating layer, and a third through-hole and a fourth through-hole that penetrate the third insulating layer;

the source electrode of the first transistor is electrically connected to the first conductive portion by the third through-hole while the first conductive portion is electrically connected to the semiconductor layer of the first transistor by the first through-hole; and

the drain electrode of the first transistor is electrically connected to the second conductive portion by the fourth through-hole while the second conductive portion is electrically connected to the semiconductor layer of the first transistor by the second through-hole.

7. The array substrate of claim 6 , further including a first capacitor and a fifth through-hole, wherein:

the fifth through-hole penetrates the second insulating layer and the third insulating layer;

a first electrode of the first capacitor is located in the second functional layer;

a second electrode of the first capacitor is located in the third functional layer; and

the first electrode of the first capacitor is electrically connected to the drain electrode or the source electrode of the first transistor by the fifth through-hole.

8. The array substrate of claim 7 , further including a sixth through-hole and a third conductive portion, wherein:

the sixth through-hole penetrates the third insulating layer;

the third conductive portion is located in the fourth functional layer; and

the second electrode of the first capacitor is electrically connected to the third conductive portion by the sixth through-hole.

9. The array substrate of claim 7 , further including a seventh through-hole and a fourth conductive portion, wherein:

the seventh through-hole penetrates the second insulating layer;

the fourth conductive portion is located in the third functional layer; and

the first electrode of the first capacitor is electrically connected to the fourth conductive portion by the seventh through-hole.

10. The array substrate of claim 6 , further including a second transistor and an eighth through-hole, wherein:

the eighth through-hole penetrates the second insulating layer and the third insulating layer;

a semiconductor layer of the second transistor is located in the first functional layer;

a gate electrode of the second transistor is located in the second functional layer;

a source electrode and a drain electrode of the second transistor are located in the fourth functional layer; and

the source electrode or the drain electrode of the first transistor is electrically connected to the gate electrode of the second transistor by the eighth through-hole.

11. The array substrate of claim 6 , further including a third transistor, wherein:

a semiconductor layer of the third transistor is located in the first functional layer;

a gate electrode of the third transistor is located in the second functional layer; and

a source electrode and a drain electrode of the third transistor are located in the third functional layer.

12. The array substrate of claim 11 , further including a ninth through-hole, wherein:

the ninth through-hole penetrates the second insulating layer and the third insulating layer; and

the source electrode or the drain electrode of the first transistor is electrically connected to the gate electrode of the third transistor by the ninth through-hole.

13. The array substrate of claim 11 , further including a tenth through-hole and a fifth conductive portion, wherein:

the tenth through-hole penetrates the third insulating layer;

the fifth conductive portion is located in the fourth functional layer; and

the source electrode or the drain electrode of the third transistor is electrically connected to the fifth conductive portion by the tenth through-hole.

14. The array substrate of claim 11 , further including an eleventh through-hole and a sixth conductive portion, wherein:

the eleventh through-hole penetrates the second insulating layer;

the sixth conductive portion is located in the second functional layer; and

the source electrode or the drain electrode of the third transistor is electrically connected to the sixth conductive portion by the eleventh through-hole.

15. A display panel, comprising an array substrate and a light emitting functional layer located on the array substrate, wherein the array substrate comprising: a substrate; a first functional layer configured on one side of the substrate; a first insulating layer configured on the first functional layer facing away from the substrate; a second functional layer configured on the first insulating layer facing away from the substrate; a second insulating layer configured on the second functional layer facing away from the substrate; a third functional layer configured on the second insulating layer facing away from the substrate; a third insulating layer configured on the third functional layer facing away from the substrate; a fourth functional layer configured on the third insulating layer facing away from the substrate; a plurality of through-holes configured to electrically connect different functional layers, wherein the depth of any through-holes does not exceed the thickness of two adjacent insulating layers; and a plurality of pixel driving circuits, wherein a pixel driving circuit comprises a first transistor, wherein a semiconductor layer of the first transistor is located in the first functional layer, a gate electrode of the first transistor is located in the second functional layer, and a source electrode and a drain electrode of the first transistor are both located in the fourth functional layer.

16. A display device, comprising a display panel which includes an array substrate and a light emitting functional layer located on the array substrate, wherein the array substrate comprising: a substrate; a first functional layer configured on one side of the substrate; a first insulating layer configured on the first functional layer facing away from the substrate; a second functional layer configured on the first insulating layer facing away from the substrate; a second insulating layer configured on the second functional layer facing away from the substrate; a third functional layer configured on the second insulating layer facing away from the substrate; a third insulating layer configured on the third functional layer facing away from the substrate; a fourth functional layer configured on the third insulating layer facing away from the substrate; a plurality of through-holes configured to electrically connect different functional layers, wherein the depth of any through-holes does not exceed the thickness of two adjacent insulating layers; and a plurality of pixel driving circuits, wherein a pixel driving circuit comprises a first transistor, wherein a semiconductor layer of the first transistor is located in the first functional layer, a gate electrode of the first transistor is located in the second functional layer, and a source electrode and a drain electrode of the first transistor are both located in the fourth functional layer.