IP Library Granted Patent US 10,170,691
Granted Patent B2
US 10,170,691 · App. 15/187,267 · Granted Jan 1, 2019

Electronic device and method for fabricating the same

Inventors: Jong-Koo Lim (Gyeonggi-do, KR); Won-Joon Choi (Gyeonggi-do, KR); Guk-Cheon Kim (Gyeonggi-do, KR); Yang-Kon Kim (Gyeonggi-do, KR); Ku-Youl Jung (Gyeonggi-do, KR); Toshihiko Nagase (Tokyo, JP); Youngmin Eeh (Tokyo, JP); Daisuke Watanabe (Tokyo, JP); Kazuya Sawada (Tokyo, JP); Makoto Nagamine (Tokyo, JP)
Assignees: SK Hynix Inc.; TOSHIBA MEMORY CORPORATION
H01L43/08H01L43/10H01L43/12
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Quick Facts
Patent No.
US 10,170,691
App. No.
15/187,267
Granted
Jan 1, 2019
Kind
B2
Abstract

Provided is a method for fabricating an electronic device including a variable resistance element which includes a free layer formed over a substrate and having a changeable magnetization direction, a pinned layer having a pinned magnetization direction, a tunnel barrier layer interposed between the free layer and the pinned layer, and a magnetic correction layer suitable for reducing the influence of a stray field generated by the pinned layer. The method may include: cooling the substrate; and forming the magnetic correction layer over the cooled substrate.

Claims (54)

1. A method for fabricating an electronic device, comprising:

forming a variable resistance element at a first temperature; and

forming a magnetic correction layer over a pinned layer at a second temperature,

wherein the second temperature is lower than the first temperature,

wherein the variable resistance element includes a free layer provided over a substrate, a pinned layer provided over the free layer, a tunnel barrier layer interposed between the free layer and the pinned layer, and

wherein the magnetic correction layer has a magnetization direction which is anti-parallel to the pinned layer,

wherein the forming of the magnetic correction layer comprises:

(a) cooling the substrate to the second temperature;

(b) forming a first layer over the cooled substrate;

(c) forming a second layer over the first layer,

(d) repeating the forming of the first layer and the forming of the second layer M number of times; and

(e) recooling the substrate to a third temperature,

wherein the third temperature is 0K-75K, inclusive, and

where M is a positive integer.

2. The method of claim 1 ,

wherein the second temperature is at 0K-75K, inclusive.

3. The method of claim 1 , wherein the steps (b)-(e) are repeated N number of times, and

where N is a positive integer.

4. A method for fabricating an electronic device including a variable resistance element which includes a free layer formed over a substrate and having a changeable magnetization direction, a pinned layer having a pinned magnetization direction, a tunnel barrier layer interposed between the free layer and the pinned layer, and a magnetic correction layer suitable for reducing the influence of a stray field generated by the pinned layer, the method comprising:

cooling the substrate; and

forming the magnetic correction layer over the cooled substrate,

wherein the forming of the magnetic correction layer comprises:

a first step of forming a first layer, wherein the first layer includes a magnetic material;

a second step of forming a second layer over the first layer, wherein the second layer includes a non-magnetic material; and

repeating the first and the second steps M number of times,

wherein M is a positive integer.

5. The method of claim 4 , wherein the cooling of the substrate is performed at 0K-75K, inclusive.

6. The method of claim 4 , wherein the magnetic material comprises Co, Fe, Ni, or a combination thereof.

7. The method of claim 4 , wherein the non-magnetic material comprises Pt, Pd, or a combination thereof.

8. The method of claim 4 , wherein the free layer, the pinned layer, and the tunnel barrier layer are formed at a temperature of 273K or more.

9. The method of claim 4 , wherein the forming of the magnetic correction layer further comprises:

a third step of recooling the substrate after repeating the first and the second steps M number of times.

10. The method of claim 9 , wherein the third step of recooling is performed at 0K-75K, inclusive.

11. The method of claim 9 , wherein the first step, the second step, and the third step are performed at the same temperature.

12. The method of claim 9 ,

wherein M number of repetitions of the first and the second steps and one time of the third step, in combination, comprise a unit cycle,

wherein the unit cycle is repeated N number of times, and

wherein N is a positive integer.

13. The method of claim 12 , wherein N is at least 4.

14. A method for fabricating an electronic device having a multilayer thin film which is formed over a substrate and in which a plurality of first layers containing a magnetic material and a plurality of second layers containing a non-magnetic material are alternately stacked, the method comprising:

(a) cooling the substrate;

(b) forming the multilayer thin film over the cooled substrate, wherein the forming of the multilayer thin film comprises:

forming a first layer over the cooled substrate;

forming a second layer over the first layer; and

repeating the forming of the first layer and the forming of the second layer M number of times;

(c) recooling the substrate; and

(d) repeating the steps (b) and (c) N number of times,

where each of N and M is a positive integer.

15. The method of claim 14 ,

wherein N is at least 4.

16. The method of claim 14 , wherein each of the cooling of the substrate and the recooling of the substrate is performed at 0K-75K, inclusive.

17. The method of claim 14 , wherein the cooling of the substrate and the recooling of the substrate are performed at the same temperature.

18. The method of claim 14 , wherein the magnetic material includes Co, Fe, Ni, or a combination thereof.

19. The method of claim 14 , wherein the non-magnetic material includes Pt, Pd, or a combination thereof.

Assignments (5)
CHANGE OF NAME Recorded Feb 15, 2022
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 059110/0850 →
CHANGE OF NAME Recorded Jan 20, 2022
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 058711/0088 →
MERGER AND CHANGE OF NAME Recorded Jan 20, 2022
From: TOSHIBA MEMORY CORPORATION; K.K. PANGEA
To: K.K. PANGEA
Reel/Frame 058786/0085 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 12, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043848/0880 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 20, 2016
From: LIM, JONG-KOO; CHOI, WON-JOON; KIM, GUK-CHEON; KIM, YANG-KON; JUNG, KU-YOUL; NAGASE, TOSHIHIKO; EEH, YOUNGMIN; WATANABE, DAISUKE; SAWADA, KAZUYA; NAGAMINE, MAKOTO
To: SK HYNIX INC.; KABUSHIKI KAISHA TOSHIBA
Reel/Frame 039092/0133 →
Continuity (2)
Provisional Application 62288213 · Jan 28, 2016
Related Publication 20170222133A1 · Aug 3, 2017