Phase current estimation for switching power converters

1. A phase current estimator, comprising:

analog circuitry operable to generate a phase current estimate error by comparing a phase current of a switching power converter to an analog representation of an estimate of the phase current, the phase current having a sawtooth or triangular waveform; and

digital circuitry operable to revise the phase current estimate based on the phase current estimate error and a plurality of parameters associated with operation of the switching power converter, so that the phase current estimate tracks the sawtooth or triangular waveform of the phase current.

2. The phase current estimator of claim 1 , wherein the digital circuitry comprises:

a tracking unit operable to scale the phase current estimate error by different gain values during different PWM (pulse width modulation) states of a PWM cycle of the switching power converter;

a slope estimator unit operable to generate by integration a new estimate of the phase current based on the different PWM states of the PWM cycle and voltage parameters associated with operation of the switching power converter; and

a slope correcting unit operable to correct for integration errors in the phase current estimate error.

3. The phase current estimator of claim 2 , wherein the tracking unit is operable to:

scale the phase current estimate error by a first gain value during an on PWM state in which a PWM pulse is activate for a first part of the PWM cycle and the phase current has a positive slope;

scale the phase current estimate error by a second gain value during an off PWM state in which the PWM pulse is deactivate for an second part of the PWM cycle and the phase current has a negative slope; and

scale the phase current estimate error by a third gain value during a transition PWM state between the on and off PWM states and the phase current transitions from a positive ramp to a negative ramp.

4. The phase current estimator of claim 3 , wherein the second gain value is greater than the first and third gain values so that the phase current estimate error is scaled by a larger value during the off PWM state of the PWM cycle than during the on and transition PWM states of the PWM cycle.

5. The phase current estimator of claim 2 , wherein the slope estimator unit and the slope correcting unit are enabled if the switching power converter is operating at a high switching frequency at which the phase current changes rapidly from a positive ramp to a negative ramp, and wherein the slope estimator unit and the slope correcting unit are disabled if the switching power converter is in a high impedance mode or if the switching power converter is operating at a low switching frequency at which the phase current changes slowly from a positive ramp to a negative ramp.

6. The phase current estimator of claim 2 , wherein the slope estimator unit is operable to:

generate a first phase current slope estimate of (V_in−V_0)/L during an on PWM state in which a PWM pulse is activate for a first part of the PWM cycle and the phase current has a positive slope, wherein V_in is an input voltage of the switching power converter, V_0 is an output voltage of the switching power converter and L is the inductance of an inductor coupled between the phase under analysis and a load driven by the switching power converter;

generate a second phase current slope estimate of (−V_0)/L during an off PWM state in which the PWM pulse is deactivate for an second part of the PWM cycle and the phase current has a negative slope; and

generate a third phase current slope estimate of (−V_0−V_d)/L during high impedance when the phase current is higher than a predetermined value, wherein V_d is a body diode voltage drop of the phase.

7. The phase current estimator of claim 2 , wherein the slope correcting unit is operable to:

integrate and scale the phase current estimate error by a first gain value during an off PWM state in which a PWM pulse is deactivate for an second part of the PWM cycle and the phase current has a negative slope; and

scale a previously integrated version of the phase current estimate error generated during the off PWM period of an immediately preceding PWM cycle by a second gain value during an on PWM state in which the PWM pulse is activate for a first part of the PWM cycle and the phase current has a positive slope.

8. The phase current estimator of claim 7 , wherein the slope correcting unit is operable to scale a previously integrated version of the phase current estimate error generated during the off PWM period of an immediately preceding PWM cycle by a third gain value for use as an initial starting point in integrating the phase current estimate error by the first gain value during the off PWM state of the PWM cycle.

9. The phase current estimator of claim 2 , wherein the digital circuitry is operable to revise the phase current estimate by combining outputs of the tracking unit, the slope estimator unit and the slope correcting unit into a combined phase estimate signal have the same sawtooth or triangular waveform as the phase current.

10. The phase current estimator of claim 2 , wherein the analog circuitry is operable to generate the phase current estimate error at a first clock rate insufficient to accurately track the phase current, and wherein the digital circuitry is operable to revise the phase current estimate at a second clock rate greater than the first clock rate so as to estimate the phase current at a higher clock rate in the digital domain than supported by the analog circuitry.

11. The phase current estimator of claim 10 , wherein the digital circuitry comprises a counter operable to accumulate the combined phase estimate signal over time at the second clock rate to provide the phase current estimate for the next PWM cycle.

12. The phase current estimator of claim 11 , wherein the digital circuitry comprises a decimator operable to down-sample the phase current estimate provided by the counter at the first clock rate for input to a DAC of the analog circuitry, the DAC being operable to generate the analog representation of the phase current estimate from the down-sampled phase current estimate provided by the decimator.

13. A method of estimating a phase current of a switching power converter, the method comprising:

generating a phase current estimate error by comparing a phase current of a switching power converter to an analog representation of an estimate of the phase current, the phase current having a sawtooth or triangular waveform, and

revising the phase current estimate based on the phase current estimate error and a plurality of parameters associated with operation of the switching power converter, so that the phase current estimate tracks the sawtooth or triangular waveform of the phase current.

14. A switching power converter, comprising:

a phase operable to deliver a phase current to a load, the phase current having a sawtooth or triangular waveform;

a first control loop including a pulse width modulator (PWM) operable to switch the phase; and

a second control loop separate from the first control loop and including a phase current estimator operable to generate a phase current estimate error by comparing the phase current to an analog representation of an estimate of the phase current, and to revise the phase current estimate based on the phase current estimate error and a plurality of parameters associated with operation of the switching power converter, so that the phase current estimate tracks the sawtooth or triangular waveform of the phase current.

15. The switching power converter of claim 14 , further comprising:

an estimator fault detection unit operable to compare the phase current to the phase current estimate to determine whether a difference between the phase current and the phase current estimate exceeds a threshold for indicating substandard phase current estimation.

16. The switching power converter of claim 15 , wherein the phase current estimate has a positive slope component and a negative slope component, and wherein the estimator fault detection unit is operable to determine whether the difference between the phase current and the positive slope component exceeds a first threshold indicating a positive slope error in the phase current and whether the difference between the phase current and the negative slope component exceeds a second threshold indicating a negative slope error in the phase current.

17. The switching power converter of claim 14 , wherein the phase current estimator comprises:

a tracking unit operable to scale the phase current estimate error by different gain values during different PWM (pulse width modulation) states of a PWM cycle of the switching power converter;

a slope estimator unit operable to generate by integration a new estimate of the phase current based on the different PWM states of the PWM cycle and voltage parameters associated with operation of the switching power converter; and

a slope correcting unit operable to correct for integration errors in the phase current estimate error.

18. The switching power converter of claim 17 , wherein the tracking unit is operable to:

scale the phase current estimate error by a first gain value during an on PWM state in which a PWM pulse is activate for a first part of the PWM cycle and the phase current has a positive slope;

scale the phase current estimate error by a second gain value during an off PWM state in which the PWM pulse is deactivate for an second part of the PWM cycle and the phase current has a negative slope; and

scale the phase current estimate error by a third gain value during a transition PWM state between the on and off PWM states and the phase current transitions from a positive ramp to a negative ramp.

19. The switching power converter of claim 17 , wherein the slope correcting unit is operable to:

integrate and scale the phase current estimate error by a first gain value during an off PWM state in which a PWM pulse is deactivate for an second part of the PWM cycle and the phase current has a negative slope; and

scale a previously integrated version of the phase current estimate error generated during the off PWM period of an immediately preceding PWM cycle by a second gain value during an on PWM state in which the PWM pulse is activate for a first part of the PWM cycle and the phase current has a positive slope.

20. The switching power converter of claim 14 , wherein analog circuitry of the phase current estimator is operable to generate the phase current estimate error at a first clock rate insufficient to accurately track the phase current, and wherein digital circuitry of the phase current estimator is operable to revise the phase current estimate at a second clock rate greater than the first clock rate so as to estimate the phase current at a higher clock rate in the digital domain than supported by the analog circuitry.

21. A method of operating a switching power converter, the method comprising:

delivering a phase current to a load via a phase of the switching power converter, the phase current having a sawtooth or triangular waveform;

switching the phase via a pulse width modulator (PWM) included in a first control loop of the switching power converter; and

via a second control loop of the switching power converter which is separate from the first control loop, generating a phase current estimate error by comparing the phase current to an analog representation of an estimate of the phase current, and revising the phase current estimate based on the phase current estimate error and a plurality of parameters associated with operation of the switching power converter, so that the phase current estimate tracks the sawtooth or triangular waveform of the phase current.