Semiconductor integrated circuit, latch circuit, and flip-flop circuit
View Patent ↗A semiconductor integrated circuit connected between a first node and a second node includes first to fourth transistors. When a signal at the second node changes, the fourth transistor is turned on, and a potential obtained by shifting a third potential by the threshold of the fourth transistor is applied to the gate of the second transistor.
1. A latch circuit comprising a semiconductor integrated circuit as a latch feedback unit, the semiconductor integrated circuit connected between a first node and a second node, the semiconductor integrated circuit comprising:
a first transistor of a first conductivity type located between the first node and a first potential node to which a first potential is applied;
a second transistor of a second conductivity type located between the first node and a second potential node to which a second potential is applied, and having a gate connected to the second node;
a third transistor of the first conductivity type located between a gate of the first transistor and the second node; and
a fourth transistor of the second conductivity type located between the gate of the second transistor and the second node,
wherein a gate of the third transistor is connected to a fourth node between the gate of the second transistor and the fourth transistor,
a gate of the fourth transistor is connected to a fifth node between the gate of the first transistor and the third transistor,
when a signal at the second node changes to turn on the first transistor, a third potential for turning on the third transistor is applied to the gate of the third transistor, and a potential obtained by shifting the third potential by a threshold of the third transistor is applied to the gate of the first transistor, and
when the signal at the second node changes to turn on the second transistor, a fourth potential for turning on the fourth transistor is applied to the gate of the fourth transistor, and a potential obtained by shifting the fourth potential by a threshold of the fourth transistor is applied to the gate of the second transistor,
the latch circuit receiving an input signal and a clock signal and outputting a latch signal, the latch circuit comprising:
a first inverter that inverts the input signal and outputs an inverted input signal;
a control switch that interrupts or transmits the inverted input signal of the first inverter, based on the clock signal;
a second inverter that receives a signal output from the control switch, inverts the signal output from the control switch, and outputs an inverted signal output from the control switch as the latch signal; and
an auxiliary circuit including a seventh transistor having a gate to which the output signal of the first inverter is applied, and an eighth transistor having a gate to which the clock signal is applied, and connected in series with the seventh transistor,
wherein the latch feedback unit is configured to receive the latch signal at the second node and feedback the latch signal to an input of the second inverter via the first node,
the control switch is composed of one transistor, and
the auxiliary circuit directly propagates the output signal of the first inverter to an output signal of the latch circuit, when the control switch transmits the output signal of the first inverter.