Memory devices, systems and methods employing command/address calibration
During a command/address calibration mode, a memory controller may transmit multiple cycles of test patterns as signals to a memory device. Each cycle of test pattern signals may be transmitted at an adjusted relative phase with respect to a clock also transmitted to the memory device. The memory device may input the test pattern signals at a timing determined by the clock, such as rising and/or falling edges of the clock. The test pattern as input by the memory device may be sent to the memory controller to determine if the test pattern was successfully transmitted to the memory device during the cycle. Multiple cycles of test pattern transmissions are evaluated to determine a relative phase of command/address signals with respect to the clock for transmission during operation of the system.
1. A method of calibrating communication over a command/address bus of a memory device, comprising:
sending a clock signal over a clock signal line;
sending a calibration enabling command through command/address terminals at a first rising edge and a first falling edge of the clock signal, wherein the command/address terminals comprise CA 0 , CA 1 , CA 2 , CA 3 , CA 4 , CA 5 , CA 6 , CA 7 , CA 8 and CA 9 ;
sending a first command/address signal through at least some of the command/address terminals with a second rising edge of the clock signal to cause generation of first information, wherein the first command/address signal and the second rising edge of the clock signal have a first phase difference;
sending a second command/address signal through the at least some of the command/address terminals with a second falling edge of the clock signal to cause generation of second information, wherein the second command/address signal and the second falling edge of the clock signal have a second phase difference;
receiving the first information and the second information through a first set of data terminals and a second set of data terminals respectively;
sending a third command/address signal through the at least some of the command/address terminals with a third rising edge of the clock signal to cause generation of third information, wherein the third command/address signal and third rising edge of the clock signal have a third phase difference;
sending a fourth command/address signal through the at least some of the command/address terminals with a third falling edge of the clock signal to cause generation of fourth information, wherein the fourth command/address signal and third falling edge of the clock signal have a fourth phase difference; and
receiving the third information and the fourth information through the first set of data terminals and the second set of data terminals respectively;
wherein the first phase difference and the third phase difference are different from each other, and the second phase difference and the fourth phase difference are different from each other.
2. The method of claim 1 , wherein the calibration enabling command has logic level of L, L, L, L, H, L, L, H, L, and H for CA 0 , CA 1 , CA 2 , CA 3 , CA 4 , CA 5 , CA 6 , CA 7 , CA 8 and CA 9 respectively at the first rising edge and at the first falling edge of the clock signal.
3. The method of claim 1 , wherein the method further includes sending a calibration disabling command through the command/address terminals at a fourth rising edge and at a fourth falling edge of the clock signal.
4. The method of claim 3 , wherein the calibration disabling command has logic level of L, L, L, L, L, H, L, H, L, and H for CA 0 , CA 1 , CA 2 , CA 3 , CA 4 , CA 5 , CA 6 , CA 7 , CA 8 and CA 9 respectively at the fourth rising edge and at the fourth falling edge of the clock signal.
5. The method of claim 1 , wherein the at least some of the command/address terminals are CA 0 , CA 1 , CA 2 , CA 3 , CA 5 , CA 6 , CA 7 and CA 8 .
6. The method of claim 1 , wherein the at least some of the command/address terminals are CA 0 , CA 1 , CA 2 , CA 3 , CA 4 , CA 5 , CA 6 , CA 7 , CA 8 and CA 9 .
7. The method of claim 1 , wherein the first set of data terminals includes DQ 0 , DQ 2 , DQ 4 , DQ 6 , DQ 8 , DQ 10 , DQ 12 and DQ 14 .
8. The method of claim 1 , wherein the second set of data terminals includes DQ 1 , DQ 3 , DQ 5 , DQ 7 , DQ 9 , DQ 11 , DQ 13 and DQ 15 .
9. The method of claim 1 , wherein the first set of data terminals includes DQ 0 , DQ 2 , DQ 4 , DQ 6 , DQS 0 , DQ 8 , DQ 10 , DQ 12 , DQ 14 and DQS 1 .
10. The method of claim 1 , wherein the second set of data terminals includes DQ 1 , DQ 3 , DQ 5 , DQ 7 , /DQS 0 , DQ 9 , DQ 11 , DQ 13 , DQ 15 and /DQS 1 .