Stacked switch circuit having shoot through current protection

1. An apparatus, comprising:

a stacked bi-directional switch circuit having protection circuitry to prevent shoot through current when the switch is in an off state and respective voltages at the input/output terminals of the switch change such that before the change one of the input/output terminals of the switch has the higher voltage and after the change the other input/output terminal of the switch has the higher voltage, the protection circuitry to, during the change, keep a first of the transistors in the switch's current path that was off prior to the change off at least until a second of the transistors in the switch's current path is turned off in response to the change, an isolated internal node of the bi-directional switch circuit that resides along the current path being coupled to a first respective channel end of both the first and second transistors, a first of the input/output terminals coupled to a second respective channel end of the first transistor, a second of the input/output terminals coupled to a second respective channel end of the second transistor, the isolated internal node not being coupled to any nodes other than the first respective channel end of both the first and second transistors, the switch's current path flowing through the respective channels of both the first and second transistors.

2. The apparatus of claim 1 wherein when the stacked bi-directional switch circuit is in the off state the protection circuitry keeps off a transistor in the switch's current path that was off in a first steady state when the one terminal of the switch had the higher voltage until another transistor that will be off in a second steady state when the other terminal of the switch has the higher voltage.

3. The apparatus of claim 1 wherein the stacked bi-directional switch circuit comprises circuitry to, when the stacked bi-directional switch circuit is in the off state, apply a higher of the respective voltages at the terminals of the switch to a gate of a transistor in the switch's current path at the terminal of the switch that receives the higher of the respective voltages.

4. The apparatus of claim 3 wherein the stacked bi-directional switch circuit comprises circuitry to, when the stacked bi-directional switch circuit is in the off state, apply the higher of the respective voltages less a second voltage to a gate of another transistor in the switch's current path that receives a lesser of the respective voltages at the terminals of the switch.

5. The apparatus of claim 4 wherein application of the higher of the respective voltages less the second voltage to the gate of the another transistor prevents the other transistor from exceeding a maximum rating.

6. The computing system of claim 1 wherein the terminals are respectively coupled to first and second I/Os of a semiconductor chip that the stacked bi-directional switch is integrated within.

7. An apparatus, comprising:

a stacked bi-directional switch circuit having protection circuitry to prevent shoot through current when the switch is in an off state and respective voltages at the input/output terminals of the switch change such that before the change one of the input/output terminals of the switch has the higher voltage and after the change the other input/output terminal of the switch has the higher voltage, wherein, the stacked bi-directional switch circuit has first and second halves that mirror each other and the protection circuitry couples the first and second halves, the protection circuitry to, during the change, keep a first of the transistors in the switch's current path that was off prior to the change off at least until a second of the transistors in the switch's current path is turned off in response to the change, an isolated internal node of the bi-directional switch circuit that resides along the current path being coupled to a first respective channel end of both the first and second transistors, a first of the input/output terminals coupled to a second respective channel end of the first transistor, a second of the input/output terminals coupled to a second respective channel end of the second transistor, the isolated internal node not being coupled to any nodes other than the first respective channel end of both the first and second transistors, the switch's current path flowing through the respective channels of both the first and second transistors.

8. The apparatus of claim 7 wherein when the stacked bi-directional switch circuit is in the off state the protection circuitry keeps off a transistor in the switch's current path that was off in a first steady state when the one terminal of the switch had the higher voltage until another transistor that will be off in a second steady state when the other terminal of the switch has the higher voltage.

9. The apparatus of claim 7 wherein the stacked bi-directional switch circuit comprises circuitry to, when the stacked switch circuit is in the off state, apply a higher of the respective voltages at the terminals of the switch to a gate of a transistor in the switch's current path at the terminal of the switch that receives the higher of the respective voltages.

10. The apparatus of claim 9 wherein the stacked bi-directional switch circuit comprises circuitry to, when the stacked bi-directional switch circuit is in the off state, apply the higher of the respective voltages less a second voltage to a gate of another transistor in the switch's current path that receives a lesser of the respective voltages at the terminals of the switch.

11. The apparatus of claim 10 wherein application of the higher of the respective voltages less the second voltage to the gate of the another transistor prevents the other transistor from exceeding a maximum rating.

12. The computing system of claim 7 wherein the terminals are respectively coupled to first and second I/Os of a semiconductor chip that the stacked bi-directional switch is integrated within.

13. A computing system, comprising:

one or more processing cores;

a system memory;

a memory controller coupled to the system memory;

power supply circuitry, the power supply circuitry comprising a stacked bi-directional switch circuit having protection circuitry to prevent shoot through current when the switch is in an off state and respective voltages at the input/output terminals of the switch change such that before the change one of the input/output terminals of the switch has the higher voltage and after the change the other input/output terminal of the switch has the higher voltage, the protection circuitry to, during the change, keep a first of the transistors in the switch's current path that was off prior to the change off at least until a second of the transistors in the switch's current path is turned off in response to the change, an isolated internal node of the bi-directional switch circuit that resides along the current path being coupled to a first respective channel end of both the first and second transistors, a first of the input/output terminals coupled to a second respective channel end of the first transistor, a second of the input/output terminals coupled to a second respective channel end of the second transistor, the isolated internal node not being coupled to any nodes other than the first respective channel end of both the first and second transistors, the switch's current path flowing through the respective channels of both the first and second transistors.

14. The computing system of claim 13 wherein when the stacked bi-directional switch circuit is in the off state the protection circuitry keeps off a transistor in the switch's current path that was off in a first steady state when the one terminal of the switch had the higher voltage until another transistor that will be off in a second steady state when the other terminal of the switch has the higher voltage.

15. The computing system of claim 13 wherein the stacked switch circuit comprises circuitry to, when the stacked bi-directional switch circuit is in the off state, apply a higher of the respective voltages at the terminals of the switch to a gate of a transistor in the switch's current path at the terminal of the switch that receives the higher of the respective voltages.

16. The computing system of claim 15 wherein the stacked bi-directional switch circuit comprises circuitry to, when the stacked bi-directional switch circuit is in the off state, apply the higher of the respective voltages less a second voltage to a gate of another transistor in the switch's current path that receives a lesser of the respective voltages at the terminals of the switch.

17. The computing system of claim 16 wherein application of the higher of the respective voltages less the second voltage to the gate of the another transistor prevents the other transistor from exceeding a maximum rating.

18. The computing system of claim 13 wherein the terminals are respectively coupled to first and second I/Os of a semiconductor chip that the stacked bi-directional switch is integrated within.