Semiconductor device with a variable-width vertical channel formed through a plurality of semiconductor layers
View Patent ↗Semiconductor devices and manufacturing methods are provided for making channel and gate lengths independent from lithography. Also, semiconductor devices and manufacturing methods are provided for increasing resistivity between drain and channel to allow for higher voltage operation. For example, a semiconductor device includes a first doped layer implanted in a semiconductor substrate forming one of a source or a drain and a gate metal layer disposed over the first doped layer. The semiconductor device further includes a second doped layer disposed over the gate metal forming the other the source or the drain, where the first doped layer, the gate metal layer and the second doped layer form a vertical stack of layers of the semiconductor device. The semiconductor device further includes a conduction channel formed in a trench that extends vertically through the vertical stack of layers and terminates at the semiconductor substrate.
1. A semiconductor device, comprising:
a first doped layer implanted in a semiconductor substrate forming one of a source or a drain;
a first dielectric layer disposed over the first doped layer;
a gate metal layer disposed over the first dielectric layer;
a second dielectric layer disposed over the gate metal layer;
a second doped layer disposed over the second dielectric layer forming the other of the source or the drain, wherein the first doped layer, the first dielectric layer, the gate metal layer, the second dielectric layer, and the second doped layer form a vertical stack of layers of the semiconductor device; and
a conduction channel formed in a trench that extends vertically through the first dielectric layer, the gate metal layer, and the second dielectric layer, wherein a width of the conduction channel at the gate metal layer is smaller than a width of the conduction channel at the first dielectric layer underneath the gate metal layer.
2. The semiconductor device of claim 1 , wherein a thickness of the conduction channel at the second dielectric layer is smaller than a thickness of the conduction channel at the first dielectric layer.
3. The semiconductor device of claim 1 , further comprising:
a gate isolation layer arranged between the first dielectric layer and the second dielectric layer, encompassing the gate metal layer.
4. The semiconductor device of claim 1 , wherein the conduction channel is separated from the gate metal layer and the second dielectric layer by a gate oxide.
5. The semiconductor device of claim 1 , wherein a width of the conduction channel at the second dielectric layer is substantially equal to the width of the conduction channel at the gate metal layer and is smaller than the width of the conduction channel at the first dielectric layer.
6. The semiconductor device of claim 5 , further comprising a silicon pad formed on top of the conduction channel and inside the second doped layer.
7. The semiconductor device of claim 6 , wherein a width of the silicon pad is substantially equal to the width of the conduction channel at the first dielectric layer.
8. The semiconductor device of claim 1 , wherein the trench and the conduction channel extend vertically through the first doped layer and terminate at the semiconductor substrate.
9. The semiconductor device of claim 1 , wherein the trench and the conduction channel extend vertically and partially through the first doped layer.
10. The semiconductor device of claim 1 , wherein the trench and the conduction channel extend vertically and partially through the second doped layer.
11. The semiconductor device of claim 1 , wherein the trench and the conduction channel extend vertically through the second doped layer and terminate at a top surface of the second doped layer.
12. The semiconductor device of claim 1 , wherein the semiconductor device is a laterally diffused metal oxide semiconductor (LDMOS) and the conduction channel at the first dielectric layer increases resistance to allow higher voltage operation of the LDMOS.
13. A semiconductor device, comprising:
a first doped layer implanted in a semiconductor substrate forming one of a source or a drain;
a first dielectric layer disposed over the first doped layer;
a gate metal layer disposed over the first dielectric layer;
a second doped layer disposed over the gate metal layer forming the other of the source or the drain, wherein the first doped layer, the first dielectric layer, the gate metal layer, and the second doped layer form a vertical stack of layers of the semiconductor device; and
a conduction channel formed in a trench that extends vertically through the first dielectric layer and the gate metal layer, wherein a width of the conduction channel at the gate metal layer is smaller than a width of the conduction channel at the first dielectric layer underneath the gate metal layer.
14. The semiconductor device of claim 13 , further comprising:
a second dielectric layer disposed over the gate metal layer, wherein the trench and the conduction channel extend vertically through the second dielectric layer.
15. The semiconductor device of claim 14 , wherein the conduction channel is separated from the gate metal layer and the second dielectric layer by a gate oxide.
16. The semiconductor device of claim 13 , wherein the conduction channel includes a silicon material that is doped relatively lightly with respect to the first and second doped layers.
17. The semiconductor device of claim 13 , wherein the gate metal layer is deposited using atomic layer deposition.
18. The semiconductor device of claim 13 , wherein:
the trench and the conduction channel extend vertically through the first doped layer and terminate at the semiconductor substrate, and
the trench and the conduction channel extend vertically through the second doped layer and terminate at a top surface of the second doped layer.
19. The semiconductor device of claim 13 , wherein the trench and the conduction channel extend vertically and partially through the first doped layer.
20. The semiconductor device of claim 13 , wherein the trench and the conduction channel extend vertically and partially through the second doped layer.