Lock-free first in, first out memory queue architecture

1. A method, implemented at least in part by one or more computing devices, of synchronizing a plurality of writer threads on a circular array, the circular array comprised of a plurality of memory chunks, each memory chunk mapped to a storage cell of a memory storage device, the method comprising:

reserving, by a first writer thread of the plurality of writer threads, one or more memory chunks of the circular array for a data message associated with the first writer thread, wherein a first write count value corresponding to the memory chunks reserved by the first writer thread is mutually exclusive of one or more write count values corresponding to memory chunks reserved by writer threads other than the first writer thread; and

writing, by the first writer thread, the data message associated therewith to the memory chunks of the circular array reserved thereby when a read count value representing a current index of a reader thread on the circular array is less than one iteration of the circular array from the first write count value.

2. The method of claim 1 , wherein the memory chunks of the circular array reserved by the first writer thread are continuous in the circular array.

3. The method of claim 1 , further comprising:

reserving, by a second writer thread of the plurality of writer threads, one or more memory chunks of the circular array for a data message associated with the second writer thread, wherein the second writer thread is different from the first writer thread, wherein a second write count value corresponding to the memory chunks reserved by the second writer thread is mutually exclusive of the first write count value and mutually exclusive of the one or more write count values corresponding to memory chunks reserved by writer threads other than the second writer thread and the first writer thread; and

writing, by the second writer thread, the data message associated therewith to the memory chunks of the circular array reserved thereby when the read count value is less than one iteration of the circular array from the second write count value.

4. The method of claim 3 , further comprising atomically incrementing, by each of the plurality of writer threads, the write count values corresponding to the memory chunks reserved thereby by a number of the memory chunks required for storing the data messages associated therewith.

5. The method of claim 3 , wherein the first writer thread performs said reserving thereby and said writing thereby concurrently with the second writer performing said reserving thereby and said writing thereby.

6. The method of claim 1 , further comprising reading, by the reader thread, the data message associated with the first writer thread when the read count value represents the index of the memory chunks of the circular array reserved by the first writer thread, wherein the data messages each comprise a real-time data value corresponding to a process device within a continuous process, said continuous process including a supervisory control and data acquisition (SCADA) system.

7. The method of claim 1 , further comprising determining, by the first writer thread, a starting index of the one or more memory chunks reserved thereby as a function of a size of the circular array.

8. The method of claim 7 , further comprising determining, by the first writer thread, an address of the memory chunks of the circular array reserved thereby as a function of the starting index and a size of the memory chunks.

9. The method of claim 1 , further comprising spinning the first writer thread when the read count value is one iteration or more of the circular array from the first write count value.

10. A computer readable storage device having processor readable instructions stored thereon including instructions that, when executed by a processor, implement a method of coordinating a plurality of writer threads on a queue, comprising:

incrementing, by each writer thread of the plurality of writer threads, a write counter as a function of a size of a data message of each writer thread, wherein each writer thread is associated with a value of the write counter incremented thereby, and wherein the write counter value associated with each writer thread is mutually exclusive of the write counter values associated with every other writer thread of the plurality of writer threads;

reserving, by each writer thread, one or more memory chunks for the data message thereof, wherein the memory chunks comprise the queue, and wherein the memory chunks reserved by each writer thread have an element identifier within the queue of the modulus of the write counter value associated therewith and a size of the queue; and

writing, by each writer thread, the data message thereof to the memory chunks of the queue reserved thereby when a read count value representing a current position of a reader thread on the queue is less than one iteration of the queue therefrom.

11. The computer readable storage device of claim 10 , wherein the memory chunks reserved by each writer thread are continuous within the queue.

12. The computer readable storage device of claim 10 , wherein each writer thread performs said incrementing sequentially, and wherein each writer thread performs said reserving and said writing concurrently.

13. The computer readable storage device of claim 10 , the instructions including instructions that, when executed by the processor, implement the method of coordinating the plurality of writer threads on the queue, the method further comprising reading, by the reader thread, the data messages stored in each memory chunk having data messages written thereto by the plurality of writer threads, wherein the data messages each comprise a real-time data value corresponding to a process device within a continuous process, said continuous process including a supervisory control and data acquisition (SCADA) system.

14. The computer readable storage device of claim 10 , the instructions including instructions that, when executed by the processor, implement the method of coordinating the plurality of writer threads on the queue, the method further comprising determining, by each writer thread, a starting index of the memory blocks reserved thereby as a function of a size of the queue.

15. The computer readable storage device of claim 14 , the instructions including instructions that, when executed by the processor, implement the method of coordinating the plurality of writer threads on the queue, the method further comprising determining, by each writer thread, an address of the memory chunks reserved thereby as a function of the determined starting index and a size of the memory chunks.

16. The computer readable storage device of claim 14 , the instructions including instructions that, when executed by the processor, implement the method of coordinating the plurality of writer threads on the queue, the method further comprising spinning each writer thread when the read count value is one iteration or more of the queue from the write count value of each writer thread.

17. A computing device comprising:

a processor; and

one or more processor-executable instructions stored on a computer-readable storage medium of the computing device, said processor-executable instructions including instructions that, when executed by the processor, provide:

an array comprised of a plurality of memory chunks, wherein each of the memory chunks represents one or more contiguous memory addresses in an address space, wherein the array has a predefined size, and wherein the array is adapted for a first-in, first-out utilization of the memory chunks;

a write chunk counter comprising an index for a plurality of writer threads on the array, wherein the write chunk counter is adapted to provide a value to each writer thread that is mutually exclusive of the value provided to every other writer thread of the plurality of writer threads for reserving one or more of the memory chunks;

a read chunk counter comprising an index and a number of iterations of a reader thread on the array,

wherein the memory chunks are adapted to have a data message associated with each of the writer threads written thereto by the writer threads when the read chunk counter is less than one iteration of the array from the index of the writer threads.

18. The computing device of claim 17 , wherein the memory chunks are adapted to have the data messages associated with each of the writer threads written thereto concurrently.

19. The computing device of claim 17 , wherein the data messages each comprise a real-time data value corresponding to a process device within a continuous process, said continuous process including a supervisory control and data acquisition (SCADA) system.

20. The computing device of claim 17 , wherein the memory chunks are adapted to store the data messages associated with a particular writer thread of the plurality of writer threads until the read chunk counter is less than one iteration of the array from the write chunk value of the particular writer thread.