Systems and methods for thermal conduction using S-contacts
An integrated circuit architecture that provides a path having relatively low thermal resistance between one or more electronic devices and one or more thermal structures formed on an insulator layer on a substrate. Independent parallel thermal conduction paths are provided through the insulator layer, such as a buried oxide (“BOX”) layer, to allow heat to flow from the substrate layer to a thermal structure disposed upon the BOX layer. In some cases, the substrate is a silicon substrate layer supporting the thermal structure and a heat source, such as an electronic device (e.g., power amplifier, transistor, diode, resistor, etc.).
1. A semiconductor integrated circuit comprising:
(a) a heat source fabricated within the semiconductor integrated circuit;
(b) a semiconductor substrate fabricated within the semiconductor integrated circuit providing an electrical base upon which the heat source is fabricated;
(c) an insulator layer within the semiconductor integrated circuit disposed on the semiconductor substrate;
(d) a thermal structure within the semiconductor integrated circuit disposed on the insulator layer; and
(e) a plurality of substrate contacts (“S-contacts”) penetrating the insulator layer to provide a thermal conduction path from the substrate to the thermal structure and spaced over an area that underlies the thermal structure to provide a thermal conduction path.
2. Claim 1 , wherein at least some of the S-contacts are not directly under the thermal structure.
3. The semiconductor structure of claim 1 , further comprising at least one heat source upon the insulator layer, each heat source being spaced apart from the thermal structure.
4. The semiconductor structure of claim 1 , wherein the thermal structure comprises a plurality of thermally conductive layers.
5. The semiconductor structure of claim 4 , wherein at least some of the layers of the thermal structure comprise silicon, aluminum, tungsten, and/or copper.
6. The semiconductor structure of claim 1 , wherein the plurality of S-contacts comprises at least 100 such S-contacts.
7. The semiconductor structure of claim 1 , wherein the plurality of S-contacts comprises at least 500 such S-contacts.
8. The semiconductor structure of claim 1 , wherein the plurality of S-contacts comprises at least 1000 such S-contacts.
9. The semiconductor structure of claim 1 , wherein the plurality of S-contacts comprises at least 5000 such S-contacts.
10. The semiconductor structure of claim 1 , wherein the plurality of S-contacts are independent parallel thermal conduction paths between the substrate and the thermal structure.
11. The semiconductor structure of claim 1 , wherein the plurality of S-contacts has a density such that at least approximately 15% of the area that underlies the thermal structure is thermally coupled through to the substrate.
12. The semiconductor structure of claim 1 , wherein the plurality of S-contacts has a density such that a thermal resistance between the thermal structure and the substrate is less than about 26.1 Watts per meter Kelvin.