Pseudo-random chopper amplifier
A chopper stabilized amplifier that utilizes a multi-frequency chopping signal to reduce chopping artifacts. By utilizing a multi-frequency chopping signal, the amplifier DC offset and flicker noise are translated to the higher chopping frequencies but are also smeared, or spread out in frequency and consequently lowered in amplitude. This lower amplitude signal allows for less stringent filtering requirements.
1. An apparatus comprising:
a first modulator comprising a plurality of modulator switches driven by non-overlapping signals and a plurality of outputs, configured to:
modulate, via the plurality of modulator switches, an amplitude of a differential input signal at multiple frequencies; and
generate a differential modulated signal;
a differential amplifier comprising a positive input, a negative input, a positive output, and a negative output, configured to:
receive, at the positive input and the negative input, the differential modulated signal;
amplify the differential modulated signal;
generate a differential amplified signal; and
output, at the positive output and the negative output, the differential amplified signal;
a first input capacitor coupled between a first output of the plurality of outputs of the first modulator and the positive input of the differential amplifier;
a second input capacitor coupled between a second output of the plurality of outputs of the first modulator and the negative input of the differential amplifier;
an output capacitor coupled between the positive output of the differential amplifier and the negative output of the differential amplifier;
a first switched feedback path coupled between the positive output of a first node between the first input capacitor and the positive input of the differential amplifier, wherein the first switched feedback path comprises a first feedback capacitor in parallel with a first pair of transistors, wherein the first switched feedback path is switched by the non-overlapping signals; and
a second switched feedback path coupled between the negative output of a second node between the second input capacitor and the negative input of the differential amplifier, wherein the second feedback path comprises a second feedback capacitor in parallel with a second pair of transistors, wherein the second switched feedback path is switched by the non-overlapping signals.
2. The apparatus of claim 1 , further comprising a physiological sensor, wherein the physiological sensor is configured to generate the differential input signal, wherein the differential input signal indicates a physiological condition.
3. The apparatus of claim 2 , wherein the physiological sensor comprises one or more of an electrocardiogram (ECG), an electromyogram (EMG), or an electroencephalogram (EEG) sensor.
4. The apparatus of claim 2 , wherein the physiological sensor comprises one or more of an accelerometer, a pressure sensor, or a voltage sensor.
5. The apparatus of claim 2 , wherein the physiological sensor comprises a chopping frequency between 4 kilohertz and 10 kilohertz.
6. The apparatus of claim 1 , wherein the first pair of transistors are P-type Metal Oxide Semiconductor field effect transistors (MOSFET).
7. The apparatus of claim 1 , wherein each transistor of the first pair of transistors comprises a drain-to-source connection.
8. The apparatus of claim 1 , wherein the second pair of transistors are P-type Metal Oxide Semiconductor field effect transistors (MOSFET).
9. The apparatus of claim 1 , wherein each transistor of the second pair of transistors comprises a drain-to-source connection.
10. The apparatus of claim 1 , wherein the differential input signal comprises a frequency between 0 hertz and 100 hertz.
11. The apparatus of claim 1 , wherein the differential input signal comprises a plurality of non-uniform pulse periods.
12. The apparatus of claim 1 , wherein each modulator switch of the plurality of modulator switches is in phase with the plurality of modulator switches.
13. The apparatus of claim 1 , wherein the plurality of modulator switches switch according to a clock signal.
14. The apparatus of claim 1 , wherein a gain of the apparatus is equal to a capacitance of the first input capacitor divided by a capacitance of the first feedback capacitor.
15. The apparatus of claim 1 , wherein a gain of the apparatus is equal to a capacitance of the second input capacitor divided by a capacitance of the second feedback capacitor.
16. The apparatus of claim 1 , wherein the first switched feedback path is configured as a high-pass signal filter.
17. The apparatus of claim 1 , wherein the second switched feedback path is configured as a high-pass signal filter.
18. The apparatus of claim 1 , wherein a period associated with a first signal of the non-overlapping signals is equal to a period associated with a second signal of the non-overlapping signals.
19. The apparatus of claim 1 , wherein the non-overlapping signals are square wave signals.
20. The apparatus of claim 1 , wherein an amount of signal noise associated with one or more of the non-overlapping signals is more than an amount of signal noise associated with the differential amplified signal.