IP Library Granted Patent US 9,639,284
Granted Patent B2
US 9,639,284 · App. 15/194,461 · Granted May 2, 2017

Candidate generation for adaptive flash tuning

Inventors: Conor Maurice Ryan (Limerick, IE); Joseph Sullivan (Shannon, IE)
Assignee: NVMDURANCE LIMITED
G06F3/0616G06F3/064G06F3/0605G06F3/0634G06F3/0649G06F3/0653G06F3/0659G06F3/0664G06F3/0679G06F3/0688G06F12/0246G06F12/1009G11C16/10G11C16/16G11C16/26G11C16/349G11C29/36G11C29/38G11C29/44G11C29/50012G06F2212/1036G06F2212/2022G06F2212/7201
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Quick Facts
Patent No.
US 9,639,284
App. No.
15/194,461
Granted
May 2, 2017
Kind
B2
Abstract

The present invention includes embodiments of systems and methods for increasing the operational efficiency and extending the estimated operational lifetime of a flash memory storage device (and its component flash memory chips, LUNs and blocks of flash memory) by monitoring the health of the device and its components and, in response, adaptively tuning the operating parameters of flash memory chips during their operational lifetime, as well as employing other less extreme preventive measures in the interim, via an interface that avoids the need for direct access to the test modes of the flash memory chips. In an offline characterization phase, “test chips” from a batch of recently manufactured flash memory chips are used to simulate various usage scenarios and measure the performance effects of writing and attempting to recover (read) test patterns written with different sets of operating parameters over time (simulating desired retention periods).

Claims (22)

1. An offline characterization system that generates, during an offline characterization phase prior to the operational lifetime of a flash memory chip, an optimal set of operating parameter values associated with a LUN in the flash memory chip, wherein the flash memory chip includes one or more LUNs, each LUN includes one or more blocks of flash memory and an associated set of one or more n-bit control registers, and each control register stores the value of an operating parameter associated with that LUN, the offline characterization system comprising:

(a) a candidate generator that generates a candidate set of operating parameter values for a subset of each of the n R permutations of sets of operating parameter values, where R represents the number of control registers in each LUN of the flash memory chip;

(b) a candidate score generator that generates a candidate score for each candidate set of operating parameter values, wherein the candidate score is determined by using a model that predicts a hardware score that would be generated from hardware testing of the flash memory chip in accordance with that candidate set of operating parameter values; and

(c) a candidate selector that selects one of the candidate sets of operating parameter values as an optimal set, based upon the candidate score of each candidate set of operating parameter values.

2. The offline characterization system of claim 1 , wherein the candidate generator determines the subset of each of the n R permutations of sets of operating parameter values by:

(a) employing a mask generator to generate a plurality of masks, each mask corresponding to a set of operating parameters, wherein each operating parameter is associated either with a low mask (L) value having a range of values between 0 and ((2 n /2)−1), or a high mask (H) value having a range of values between (2 n /2) and (2 n −1); and

(b) generating a candidate set of operating parameter values for each of the 2 R mask permutations, wherein the value of each operating parameter in each candidate set is determined by generating a random number within the range of values of the low mask (L) value or high mask (H) value associated with that operating parameter.

3. The offline characterization system of claim 1 , adapted to generate an optimal set of operating parameter values for each of a plurality of health stages.

4. The offline characterization system of claim 1 , wherein

(a) the model utilized by the candidate generator is a non-linear function that generates each candidate score as a function of an input set of operating parameter values, and

(b) the candidate score represents a prediction of (i) the time that would be required to perform a write operation on the flash memory chip in accordance with the input set of operating parameter values, (ii) the time that would be required to perform an erase operation on the flash memory chip in accordance with the input set of operating parameter values, or (iii) the success or failure of a read operation that would be performed on the flash memory chip in accordance with the input set of operating parameter values.

5. A method for generating, during an offline characterization phase prior to the operational lifetime of a flash memory chip, an optimal set of operating parameter values associated with a LUN in the flash memory chip, wherein the flash memory chip includes one or more LUNs, each LUN includes one or blocks of flash memory and an associated set of one or more n-bit control registers, and each control register stores the value of an operating parameter associated with that LUN, the method comprising the following steps:

(a) generating a candidate set of operating parameter values for a subset of each of the n R permutations of sets of operating parameter values, where R represents the number of control registers in each LUN of the flash memory chip;

(b) generating a candidate score for each candidate set of operating parameter values, wherein the candidate score is determined by using a model that predicts a hardware score that would be generated from hardware testing of the flash memory chip in accordance with that candidate set of operating parameter values; and

(c) selecting one of the candidate sets of operating parameter values as an optimal set, based upon the candidate score of each candidate set of operating parameter values.

6. The method of claim 5 , further comprising the following steps to determine the subset of each of the n R permutations of sets of operating parameter values:

(a) generating a plurality of masks, each mask corresponding to a set of operating parameters, wherein each operating parameter is associated either with a low mask (L) value having a range of values between 0 and ((2 n /2)−1), or a high mask (H) value having a range of values between (2 n /2) and (2 n −1); and

(b) generating a candidate set of operating parameter values for each of the 2 R mask permutations, wherein the value of each operating parameter in each candidate set is determined by generating a random number within the range of values of the low mask (L) value or high mask (H) value associated with that operating parameter.

7. The method of claim 5 , further comprising the additional step of generating an optimal set of operating parameter values for each of a plurality of health stages.

8. The method of claim 5 , wherein

(a) the model is a non-linear function that generates each candidate score as a function of an input set of operating parameter values, and

(b) the candidate score represents a prediction of (i) the time that would be required to perform a write operation on the flash memory chip in accordance with the input set of operating parameter values, (ii) the time that would be required to perform an erase operation on the flash memory chip in accordance with the input set of operating parameter values, or (iii) the success or failure of a read operation that would be performed on the flash memory chip in accordance with the input set of operating parameter values.

Assignments (7)
PATENT SECURITY AGREEMENT Recorded Aug 6, 2024
From: RPX CORPORATION; RPX CLEARINGHOUSE LLC
To: BARINGS FINANCE LLC, AS COLLATERAL AGENT
Reel/Frame 068328/0674 →
RELEASE OF LIEN ON PATENTS Recorded Aug 5, 2024
From: BARINGS FINANCE LLC
To: RPX CORPORATION
Reel/Frame 068328/0278 →
RELEASE OF SECURITY INTEREST Recorded Oct 26, 2020
From: JEFFERIES FINANCE LLC
To: RPX CORPORATION
Reel/Frame 054486/0422 →
PATENT SECURITY AGREEMENT Recorded Oct 23, 2020
From: RPX CLEARINGHOUSE LLC; RPX CORPORATION
To: BARINGS FINANCE LLC, AS COLLATERAL AGENT
Reel/Frame 054244/0566 →
PATENT SECURITY AGREEMENT Recorded Oct 23, 2020
From: RPX CLEARINGHOUSE LLC; RPX CORPORATION
To: BARINGS FINANCE LLC, AS COLLATERAL AGENT
Reel/Frame 054198/0029 →
SECURITY INTEREST Recorded Jun 29, 2018
From: RPX CORPORATION
To: JEFFERIES FINANCE LLC
Reel/Frame 046486/0433 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 2, 2018
From: NVMDURANCE LIMITED
To: RPX CORPORATION
Reel/Frame 045094/0867 →
Continuity (4)
Continuation 14816986 · Aug 3, 2015
Provisional Application 62033077 · Aug 4, 2014
Provisional Application 62119413 · Feb 23, 2015
Related Publication 20160306571A1 · Oct 20, 2016