Method and system for mitigating the effect of write and read disturbances in solid state memory regions

1. A method for mitigating the effect of write disturbances in solid state memory, the method comprising:

receiving a request to write to a memory location of the solid state memory;

writing to the memory location in response to the request;

identifying a disturbed memory location based on a weight, wherein the weight specifies a degree to which at least the disturbed memory location is affected by performing the write to the memory location, wherein the disturbed memory location stores an ambiguous state following the write to the memory location;

identifying a memory region that comprises the disturbed memory location;

identifying an address, in the memory region, of the disturbed memory location;

generating, using a hash function, an address hash from the address;

obtaining, for the memory region, a history of disturbed memory locations comprising a set of bits;

mapping the address hash to a bit of the set of bits;

making a first determination, based on an inspection of the bit, that the history of disturbed memory locations for the memory region comprises the address hash, and based on the first determination:

clearing the history of disturbed memory locations; and

making a second determination that a wear level operation is due, and based on the second determination:

performing the wear level operation to restore the disturbed memory location to a desired state, wherein the desired state corresponds to the state of the disturbed memory location prior to the write to the memory location.

2. The method of claim 1 further comprising:

receiving a second request to write to a second memory location of the solid state memory;

writing to the second memory location in response to the second request;

identifying a second disturbed memory location based on a second weight;

identifying the memory region as further comprising the second disturbed memory location;

identifying, in the memory region, a second address of the second disturbed memory location;

generating, using the hash function, a second address hash from the second address;

mapping the second address hash to a second bit of the set of bits; and

making a third determination, based on an inspection of the second bit, that the history of disturbed memory locations for the memory region does not comprise the second address hash, and based on the third determination:

modifying the second bit to indicate that the history of disturbed memory locations comprises the second address hash.

3. The method of claim 2 , further comprising:

receiving a third request to write to a third memory location of the solid state memory;

writing to the third memory location in response to the third request;

identifying the second disturbed memory location based on a third weight;

making a fourth determination, based on another inspection of the second bit, that the history of disturbed memory locations for the memory region comprises the second address hash, and based on the fourth determination:

clearing the history of disturbed memory locations; and

making a fifth determination that a second wear level operation is due, and based on the fifth determination:

performing the second wear level operation to restore the second disturbed memory location to a second desired state.

4. The method of claim 1 , wherein making the second determination that the wear level operation is due comprises comparing a counter for a number of repeatedly disturbed memory locations, observed since the most recent wear level operation, to a specified threshold.

5. The method of claim 4 ,

wherein the counter is updated each time a repeatedly disturbed memory location is detected.

6. The method of claim 5 , wherein the update increment is adjusted based on a degree of disturbance that was caused in the disturbed memory location, by writing to the memory location.

7. The method of claim 1 , further comprising, after writing to the memory location:

identifying a second disturbed memory location based on a second weight,

wherein the second disturbed memory location is located in a second memory region, different from the first memory region;

wherein a second history of disturbed memory locations, comprising a second set of bits, is maintained for the second memory region to control wear level operations in the second memory region, based on detected repeatedly disturbed memory locations in the second memory region.

8. The method of claim 1 , wherein identifying the disturbed memory location comprises:

locating a memory location that is geometrically adjacent to the memory location where the write was performed.

9. A storage appliance, comprising:

a storage module comprising solid state memory and a storage module controller,

wherein the storage module controller is configured to:

receive a request to write to a memory location of the solid state memory;

write to the memory location in response to the request;

identify a disturbed memory location based on a weight, wherein the weight specifies a degree to which at least the disturbed memory location is affected by performing the write to the memory location, wherein the disturbed memory location stores an ambiguous state following the write to the memory location;

identify a memory region that comprises the disturbed memory location;

identify an address, in the memory region, of the disturbed memory location;

generate, using a hash function, an address hash from the address;

obtain, for the memory region, a history of disturbed memory locations comprising a set of bits;

mapping the address hash to a bit of the set of bits;

make a first determination, based on an inspection of the bit, that the history of disturbed memory locations for the memory region comprises the address hash, and based on the first determination:

clear the history of disturbed memory locations; and

make a second determination that a wear level operation is due, and based on the second determination:

perform the wear level to restore the disturbed memory location to a desired state, wherein the desired state corresponds to the state of the disturbed memory location prior to the write to the memory location.

10. The storage appliance of claim 9 , wherein the storage module controller is further configured to:

receive a second request to write to a second memory location of the solid state memory;

write to the second memory location in response to the second request;

identify a second disturbed memory location based on a second weight;

identify the memory region as further comprising the second disturbed memory location;

identify, in the memory region, a second address of the second disturbed memory location;

generate, using the hash function, a second address hash from the second address; map the second address hash to a second bit of the set of bits; and

make a third determination, based on an inspection of the second bit, that the history of disturbed memory locations for the memory region does not comprise the second address hash, and based on the third determination:

modify the second bit to indicate that the history of disturbed memory locations comprises the second address hash.

11. The storage appliance of claim 10 , wherein the storage module controller is further configured to:

receive a third request to write to a third memory location of the solid state memory;

write to the third memory location in response to the third request;

identify the second disturbed memory location based on a third weight;

make a fourth determination, based on another inspection of the second bit, that the history of disturbed memory locations for the memory region comprises the second address hash, and based on the fourth determination:

clear the history of disturbed memory locations; and

make a fifth determination that a second wear level operation is due, and based on the fifth determination:

perform the second wear level operation to restore the second disturbed memory location to a second desired state.

12. The storage appliance of claim 9 , wherein making the second determination that the wear level operation is due comprises comparing a counter for a number of repeatedly disturbed memory locations, observed since the most recent wear level operation, to a specified threshold.

13. The storage appliance of claim 12 ,

wherein the counter is updated each time a repeatedly disturbed memory location is detected; and

wherein the update increment is adjusted based on a degree of disturbance that was caused in the disturbed memory location, by writing to the memory location.

14. The storage appliance of claim 9 , wherein the storage module controller is further configured to:

identify a second disturbed memory location based on a second weight,

wherein the second disturbed memory location is located in a second memory region, different from the first memory region;

wherein a second history of disturbed memory locations, comprising a second set of bits, is maintained for the second memory region to control wear level operations in the second memory region, based on detected repeatedly disturbed memory locations in the second memory region.

15. A non-transitory computer readable medium (CRM) comprising instructions, which when executed by a storage module controller, enable the storage module controller to:

receive a request to write to a memory location of the solid state memory;

write to the memory location in response to the request;

identify a disturbed memory location based on a weight, wherein the weight specifies a degree to which at least the disturbed memory location is affected by performing the write to the memory location, wherein the disturbed memory location stores an ambiguous state following the write to the memory location;

identify a memory region that comprises the disturbed memory location;

identify an address, in the memory region, of the disturbed memory location;

generate, using a hash function, an address hash from the address;

obtain, for the memory region, a history of disturbed memory locations comprising a set of bits;

mapping the address hash to a bit of the set of bits;

make a first determination, based on an inspection of the bit, that the history of disturbed memory locations for the memory region comprises the address hash, and based on the first determination:

clear the history of disturbed memory locations;

make a second determination that a wear level operation is due, and based on the second determination:

perform the wear level operation to restore the disturbed memory location to a desired state, wherein the desired state corresponds to the state of the disturbed memory location prior to the write to the memory location.

16. The non-transitory CRM of claim 15 further comprising instructions that enable the storage module controller to:

receive a second request to write to a second memory location of the solid state memory;

write to the second memory location in response to the second request;

identify a second disturbed memory location based on a second weight;

identify the memory region as further comprising the second disturbed memory location;

identify, in the memory region, a second address of the second disturbed memory location;

generate, using the hash function, a second address hash from the second address;

map the second address hash to a second bit of the set of bits; and

make a third determination, based on an inspection of the second bit, that the history of disturbed memory locations for the memory region does not comprise the second address hash, and based on the third determination:

modify the second bit to indicate that the history of disturbed memory locations comprises the second address hash.

17. The non-transitory CRM of claim 16 , further comprising instructions that enable the storage module controller to:

receive a third request to write to a third memory location of the solid state memory;

write to the third memory location in response to the third request;

identify the second disturbed memory location based on a third weight;

make a fourth determination, based on another inspection of the second bit, that the history of disturbed memory locations for the memory region comprises the second address hash, and based on the fourth determination:

clear the history of disturbed memory locations; and

make a fifth determination that a second wear level operation is due, and based on the fifth determination:

perform the second wear level operation to restore the second disturbed memory location to a second desired state.

18. The non-transitory CRM of claim 15 , wherein making the second determination that the wear level operation is due comprises comparing a counter for a number of repeatedly disturbed memory locations, observed since the most recent wear level operation, to a specified threshold.

19. The non-transitory CRM of claim 18 ,

wherein the counter is updated each time a repeatedly disturbed memory location is detected; and

wherein the update increment is adjusted based on a degree of disturbance that was caused in the disturbed memory location, by writing to the memory location.

20. The non-transitory CRM of claim 15 , further comprising instructions that enable the storage module controller to, after writing to the memory location:

identify a second disturbed memory location based on a second weight,

wherein the second disturbed memory location is located in a second memory region, different from the first memory region;

wherein a second history of disturbed memory locations, comprising a second set of bits, is maintained for the second memory region to control wear level operations in the second memory region, based on detected repeatedly disturbed memory locations in the second memory region.