IP Library Granted Patent US 9,710,180
Granted Patent B1
US 9,710,180 · App. 15/199,092 · Granted Jul 18, 2017

Method and system for controlling wear level operations in solid state memory

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Quick Facts
Patent No.
US 9,710,180
App. No.
15/199,092
Granted
Jul 18, 2017
Kind
B1
Abstract

A method for controlling wear level operations in solid state memory. The method includes receiving a request to write to a memory location identified by a write address of the solid state memory, generating a write address hash from the write address, making a first determination that a write history for a memory region includes the write address hash, and based on the first determination: clearing the write history, storing the write address hash in the write history, and making a second determination that a wear level operation is due, and based on the second determination: performing the wear level operation.

Claims (84)

1. A method for controlling wear level operations in solid state memory, the method comprising:

receiving a request to write to a memory location identified by a write address of the solid state memory;

generating a write address hash from the write address;

making a first determination that a write history for a memory region comprises the write address hash, and based on the first determination:

clearing the write history;

storing the write address hash in the write history; and

making a second determination that a wear level operation is due, and based on the second determination:

performing the wear level operation.

2. The method of claim 1 , further comprising writing to the memory location identified by the write address.

3. The method of claim 2 , further comprising, after writing to the memory location identified by the write address, incrementing a counter of total writes.

4. The method of claim 3 , further comprising making a third determination, using the counter of total writes, that the memory region is worn, and based on the third determination, discontinuing using the memory region.

5. The method of claim 1 further comprising:

receiving a second request to write to a second memory location identified by a second write address of the solid state memory;

generating a second write address hash from the second write address;

making a third determination that the write history does not comprise the second write address hash, and based on the third determination:

storing the write address hash in the write history.

6. The method of claim 1 ,

wherein the write address hash comprises two hash values,

wherein each of the two hash values is generated by a separate hash function; and

wherein the hash functions are independent from one another.

7. The method of claim 6 , wherein each of the hash functions is configured to accept write addresses in the range of the memory region to generate hash values in the range matching the size of the write history.

8. The method of claim 1 , wherein making the second determination that the wear level operation is due comprises comparing a counter for the number of duplicate writes to a memory location, observed since the most recent wear level operation, to a specified repetitive write limit.

9. The method of claim 8 ,

wherein the counter is updated each time a duplicate write to a memory location is detected; and

wherein the update increment is adjusted based on the probability that the detected duplicate write to the memory location is a true positive.

10. A storage appliance, comprising:

storage modules comprising solid state memory,

wherein the storage appliance is configured to:

receive a request to write to a memory location in a memory region of the solid state memory, identified by a write address;

generate a write address hash from the write address;

make a first determination that a write history for the memory region comprises the write address hash, and based on the first determination:

clear the write history;

store the write address hash in the write history; and

make a second determination that a wear level operation is due, and based on the second determination:

perform the wear level operation.

11. The storage appliance of claim 10 ,

wherein the storage appliance is further configured to:

write to the memory location identified by the write address; and

after writing to the memory location identified by the write address, increment a counter of total writes.

12. The storage appliance of claim 11 ,

wherein the storage appliance is further configured to:

make a third determination, using the counter of total writes, that the memory region is worn, and based on the third determination, discontinue using the memory region.

13. The storage appliance of claim 10 ,

wherein the storage appliance is further configured to:

receive a second request to write to a second memory location identified by a second write address of the solid state memory;

generate a second write address hash from the second write address; and

make a third determination that the write history does not comprise the second write address hash, and based on the third determination:

store the write address hash in the write history.

14. The storage appliance of claim 10 ,

wherein the write address hash comprises two hash values,

wherein each of the two hash values is generated by a separate hash function;

wherein the hash functions are independent from one another; and

wherein each of the hash functions is configured to accept write addresses in the range of the memory region to generate hash values in the range matching the size of the write history.

15. The storage appliance of claim 10 , wherein making the second determination that the wear level operation is due comprises comparing a counter for the number of duplicate writes to a memory location, observed since the most recent wear level operation, to a specified repetitive write limit.

16. The storage appliance of claim 15 ,

wherein the counter is updated each time a duplicate write to a memory location is detected; and

wherein the update increment is adjusted based on the probability that the detected duplicate write to the memory location is a true positive.

17. A non-transitory computer readable medium (CRM) comprising instructions that enable a storage appliance to:

receive a request to write to a memory location of solid state memory of the storage appliance, identified by a write address;

generate a write address hash from the write address;

make a first determination that a write history for a memory region comprises the write address hash, and based on the first determination:

clear the write history;

store the write address hash in the write history; and

make a second determination that a wear level operation is due, and based on the second determination:

perform the wear level operation.

18. The non-transitory CRM of claim 17 , further comprising instructions that enable the storage appliance to:

write to the memory location identified by the write address; and

after writing to the memory location identified by the write address, increment a counter of total writes.

19. The non-transitory CRM of claim 18 , further comprising instructions that enable the storage appliance to:

make a third determination, using the counter of total writes, that the memory region is worn, and based on the third determination, discontinue using the memory region.

20. The non-transitory CRM of claim 17 further comprising instructions that enable the storage appliance to:

receive a second request to write to a second memory location identified by a second write address of the solid state memory;

generate a second write address hash from the second write address;

make a third determination that the write history does not comprise the second write address hash, and based on the third determination:

store the write address hash in the write history.

21. The non-transitory CRM of claim 17 ,

wherein the write address hash comprises two hash values,

wherein each of the two hash values is generated by a separate hash function;

wherein the hash functions are independent from one another; and

wherein each of the hash functions is configured to accept write addresses in the range of the memory region to generate hash values in the range matching the size of the write history.

22. The non-transitory CRM of claim 17 , wherein making the second determination that the wear level operation is due comprises comparing a counter for the number of duplicate writes to a memory location, observed since the most recent wear level operation, to a specified repetitive write limit.

23. The non-transitory CRM of claim 22 ,

wherein the counter is updated each time a duplicate write to a memory location is detected; and

wherein the update increment is adjusted based on the probability that the detected duplicate write to the memory location is a true positive.

Assignments (9)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (043775/0082) Recorded May 20, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 060958/0468 →
RELEASE OF SECURITY INTEREST AT REEL 043772 FRAME 0750 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 058298/0606 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
PATENT SECURITY AGREEMENT (NOTES) Recorded Sep 6, 2017
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 043775/0082 →
PATENT SECURITY AGREEMENT (CREDIT) Recorded Sep 6, 2017
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 043772/0750 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 1, 2017
From: EMC CORPORATION
To: EMC IP HOLDING COMPANY
Reel/Frame 042647/0497 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2016
From: VAN GAASBECK, RICHARD H.
To: EMC CORPORATION
Reel/Frame 039104/0017 →