Successive approximation register analog to digital converter with multiple split digital to analog convertors

1. A digital to analog convertor comprising:

an output line;

a first plurality of capacitors coupled in parallel with one another, coupled with said output line, and comprising a first least significant bit capacitor of a first capacitance value;

a second plurality of capacitors coupled in parallel with one another, coupled with said output line, and comprising a second capacitor of said first capacitance value,

wherein the first plurality of capacitors and the second plurality of capacitors have a different number of capacitors;

a third plurality of capacitors coupled in parallel with one another, coupled with said output line, and comprising a third capacitor of said first capacitance value;

a fourth plurality of capacitors coupled in parallel with one another, coupled with said output line, and comprising a smallest capacitor of said first capacitance value;

a first bridge capacitor bridging said output line between said first plurality of capacitors and said second plurality of capacitors;

a second bridge capacitor bridging said output line between said second plurality of capacitors and said third plurality of capacitors,

wherein the first plurality of capacitors, the second plurality of capacitors, the first bridge capacitor, and the second bridge capacitor form a first equivalent capacitor;

a tunable capacitor coupled in parallel with the first equivalent capacitor and the third capacitor in the third plurality of capacitors, wherein the tunable capacitor in parallel with the first equivalent capacitor has a capacitance equal to the first capacitance value; and

a third bridge capacitor bridging said output line between said third plurality of capacitors and said fourth plurality of capacitors,

wherein the first equivalent capacitor, the tunable capacitor, the third plurality of capacitors, and the third bridge capacitor form a second equivalent capacitor having a capacitance equal to the first capacitance value, and

wherein said first and second bridge capacitors are configured with different capacitive values than one another.

2. The digital to analog convertor of claim 1 , further comprising:

a first analog trim capacitor with its top plate coupled to the top plate of said first bridge capacitor and the top plate of said second capacitor of said first capacitance value.

3. The digital to analog convertor of claim 1 , further comprising:

an input voltage line, wherein said first plurality of capacitors, said second plurality of capacitors, and said third plurality of capacitors are disposed to couple to said input voltage line in a top plate sampling configuration.

4. The digital to analog convertor of claim 1 , further comprising:

an input voltage line, wherein said first plurality of capacitors, said second plurality of capacitors, and said third plurality of capacitors are disposed to couple to said input voltage line in a bottom plate sampling configuration.

5. A processing system for a capacitive sensing input device, said processing system comprising:

front end signal processing configured for receiving an input from a capacitive sensor and performing front end processing of said input to achieve a front-end processed input comprising a negative input voltage (Vinn) line and a positive input voltage line (Vinp); and

a successive approximation analog to digital convertor configured for performing analog to digital conversion of said front-end processed input and comprising:

a comparator comprising a first input coupled with the Vinn line and a second input coupled with the Vinp line;

a successive approximation register coupled with an output of said comparator and configured for converting analog outputs of said comparator to digital values;

a first plurality of capacitors coupled in parallel with one another, coupled with said Vinn line, and comprising a first least significant bit capacitor of a first capacitance value;

a second plurality of capacitors coupled in parallel with one another, coupled with said Vinn line, and comprising a second capacitor of said first capacitance value,

wherein the first plurality of capacitors and the second plurality of capacitors have a different number of capacitors;

a third plurality of capacitors coupled in parallel with one another, coupled with said Vinn line, and comprising a third capacitor of said first capacitance value;

a first bridge capacitor bridging said Vinn line between said first plurality of capacitors and said second plurality of capacitors; and

a second bridge capacitor bridging said Vinn line between said second plurality of capacitors and said third plurality of capacitors,

wherein the first plurality of capacitors and the first bridge capacitor form a first equivalent capacitor; and

a tunable capacitor coupled in parallel with the first equivalent capacitor and the second capacitor in the second plurality of capacitors,

wherein the tunable capacitor in parallel with the first equivalent capacitor has a capacitance equal to the first capacitance value,

wherein the first equivalent capacitor, the tunable capacitor, the second plurality of capacitors, and the second bridge capacitor form a second equivalent capacitor with a capacitance equal to the first capacitance value, and

wherein said first and second bridge capacitors are configured with different capacitive values than one another.

6. The processing system of claim 5 , wherein said successive approximation analog to digital convertor further comprises:

a fourth plurality of capacitors coupled in parallel with one another, coupled with said Vinp line, and comprising a matched set to said first plurality of capacitors;

a fifth plurality of capacitors coupled in parallel with one another, coupled with said Vinp line, and comprising a matched set to said second plurality of capacitors;

a sixth plurality of capacitors coupled in parallel with one another, coupled with said Vinp line, and comprising a matched set to said third plurality of capacitors;

a third bridge capacitor bridging said Vinp line between said fourth plurality of capacitors and said fifth plurality of capacitors; and

a fourth bridge capacitor bridging said Vinp line between said fifth plurality of capacitors and said sixth plurality of capacitors.

7. The processing system of claim 6 , further comprising:

a seventh plurality of capacitors coupled in parallel with one another, coupled with said Vinn line, and comprising a fourth capacitor of said first capacitance value;

an eighth plurality of capacitors coupled in parallel with one another, coupled with said Vinp line, and comprising a matched set to said seventh plurality of capacitors;

a fifth bridge capacitor bridging said Vinn line between said third plurality of capacitors and said seventh plurality of capacitors; and

a sixth bridge capacitor bridging said Vinp line between said sixth plurality of capacitors and said eighth plurality of capacitors.

8. The processing system of claim 7 , wherein:

said first and third bridge capacitors are configured with matching capacitance values; and

said second and fourth bridge capacitors are configured with matching capacitance values.

9. The processing system of claim 5 , further comprising:

a first terminating capacitor having said first capacitance value and coupled to said Vinn line in parallel with said first least significant bit capacitor.

10. The processing system of claim 5 , wherein said first plurality of capacitors, said second plurality of capacitors, and said third plurality of capacitors are disposed to couple to said Vinn line in a top plate sampling configuration.

11. The processing system of claim 5 , wherein said first plurality of capacitors, said second plurality of capacitors, and said third plurality of capacitors are disposed to couple to said Vinn line in a bottom plate sampling configuration.

12. A capacitive sensing input device comprising:

at least one capacitive sensor; and

a processing system comprising:

a successive approximation analog to digital convertor configured for performing analog to digital conversion of an input comprising a negative input voltage (Vinn) line and a positive input voltage line (Vinp), and comprising:

a comparator comprising a first input coupled with the Vinn line and a second input coupled with the Vinp line;

a successive approximation register coupled with an output of said comparator and configured for converting analog outputs of said comparator to digital values;

a first plurality of capacitors coupled in parallel with one another, coupled with said Vinn line, and comprising a first least significant bit capacitor of a first capacitance value;

a second plurality of capacitors coupled in parallel with one another, coupled with said Vinn line, and comprising a second capacitor of said first capacitance value,

wherein the first plurality of capacitors and the second plurality of capacitors have a different number of capacitors;

a third plurality of capacitors coupled in parallel with one another, coupled with said Vinn line, and comprising a third capacitor of said first capacitance value;

a first bridge capacitor bridging said Vinn line between said first plurality of capacitors and said second plurality of capacitors;

a second bridge capacitor bridging said Vinn line between said second plurality of capacitors and said third plurality of capacitors,

wherein the first plurality of capacitors and the first bridge capacitor form a first equivalent capacitor; and

a tunable capacitor coupled in parallel with the first equivalent capacitor and the second capacitor in the second plurality of capacitors,

wherein the tunable capacitor in parallel with the first equivalent capacitor has a capacitance equal to the first capacitance value,

wherein the first equivalent capacitor, the tunable capacitor, the second plurality of capacitors, and the second bridge capacitor form a second equivalent capacitor with a capacitance equal to the first capacitance value, and

wherein said first and second bridge capacitors are configured with different capacitive values than one another.

13. The capacitive sensing input device of claim 12 , wherein said successive approximation analog to digital convertor further comprises:

a fourth plurality of capacitors coupled in parallel with one another, coupled with said Vinp line, and comprising a matched set to said first plurality of capacitors;

a fifth plurality of capacitors coupled in parallel with one another, coupled with said Vinp line, and comprising a matched set to said second plurality of capacitors;

a sixth plurality of capacitors coupled in parallel with one another, coupled with said Vinp line, and comprising a matched set to said third plurality of capacitors;

a third bridge capacitor bridging said Vinp line between said fourth plurality of capacitors and said fifth plurality of capacitors; and

a fourth bridge capacitor bridging said Vinp line between said fifth plurality of capacitors and said sixth plurality of capacitors.

14. The capacitive sensing input device of claim 13 , further comprising:

a seventh plurality of capacitors coupled in parallel with one another, coupled with said Vinn line, and comprising a fourth capacitor of said first capacitance value;

an eighth plurality of capacitors coupled in parallel with one another, coupled with said Vinp line, and comprising a matched set to said seventh plurality of capacitors;

a fifth bridge capacitor bridging said Vinn line between said third plurality of capacitors and said seventh plurality of capacitors; and

a sixth bridge capacitor bridging said Vinp line between said sixth plurality of capacitors and said eighth plurality of capacitors.

15. The capacitive sensing input device of claim 14 , wherein:

said first and third bridge capacitors are configured with matching capacitance values; and

said second and fourth bridge capacitors are configured with matching capacitance values.

16. The capacitive sensing input device of claim 12 , further comprising:

a first terminating capacitor having said first capacitance value and coupled to said Vinn line in parallel with said first least significant bit capacitor.