Data transfer circuit, imaging circuit device, and electronic apparatus
A data transfer circuit that can suppress a voltage drop in a start signal without narrowing a process margin. The data transfer circuit includes N stages of register sections that are connected in series. A register section at an n th stage includes: a first transfer gate that transfers an analog signal; a second transfer gate that transfers one clock out of a clock signal, thereby generating an (n+1) th start signal for a register section at an (n+1) th stage; a control signal generation circuit that generates control signals for the first transfer gate and the second transfer gate; and a holding capacitor. The control signal generation circuit includes a third transfer gate that transfers an n th start signal that is input from a register section at an (n−1) th stage, and the third transfer gate is formed as a CMOS logic circuit.
1. A data transfer circuit, comprising
N stages of register sections that are connected in series and that respectively control transfer timings of N analogue signals, where N is an integer that is greater than or equal to 3, wherein
a register section at an n th (1<n<N) stage includes:
a first transfer gate that transfers one analogue signal out of the N analogue signals;
a second transfer gate that transfers one clock out of a clock signal, thereby generating an (n+1) th start signal for a register section at an (n+1) th stage;
a control signal generation circuit that generates control signals for the first transfer gate and the second transfer gate; and
a holding capacitor whose one end is connected to an output node of the control signal generation circuit, and that holds a voltage of the output node,
the control signal generation circuit includes a third transfer gate that transfers an n th start signal that is input from a register section at an (n−1) th stage, based on the n th start signal, and
the third transfer gate is formed as a CMOS logic circuit.
2. The data transfer circuit according to claim 1 , wherein
the control signal generation circuit includes:
a first reset transistor that resets an electric potential of an input node of the third transfer gate based on the clock signal; and
a second reset transistor that resets an electric potential of the output node based on an (n+2) th start signal that is output from a second transfer gate of the register section at the (n+1) th stage.
3. The data transfer circuit according to claim 2 , wherein
the clock signal that is input to the second transfer gate of the register section at the n th stage and a clock signal that is input to the second transfer gate of the register section at the (n+1) th stage have an inverse relation with each other.
4. The data transfer circuit according to claim 3 , wherein
the second transfer gate is formed as a CMOS logic circuit.
5. The data transfer circuit according to claim 3 , wherein
the first transfer gate is formed as a CMOS logic circuit.
6. The data transfer circuit according to claim 2 , further comprising
a reset state maintaining circuit that maintains a reset electric potential of the output node even after the second reset transistor is turned OFF, the reset electric potential resulting from resetting performed by the second reset transistor.
7. The data transfer circuit according to claim 4 , further comprising:
an NMOS transistor that is connected to the output node and ground; and
an inverting logic circuit that inverts the voltage of the output node, and supplies the inverted voltage to a control terminal of at least one of the first transfer gate and the second transfer gate and to a gate of the NMOS transistor, the first transfer gate and the second transfer gate each being formed as a CMOS logic circuit.
8. The data transfer circuit according to claim 4 , further comprising
a first inverting logic circuit that inverts the voltage of the output node, and supplies the inverted voltage to a control terminal of at least one of the first transfer gate and the second transfer gate, the first transfer gate and the second transfer gate each being formed as a CMOS logic circuit; and
a second inverting logic circuit that is connected in parallel with the first inverting logic circuit, and inverts an output from the first inverting logic circuit.
9. The data transfer circuit according to claim 1 , wherein
another end of the holding capacitor is fixed at a predetermined electric potential.
10. An imaging circuit device, comprising:
a pixel section in which a light-receiving element is disposed in each of a plurality of pixels;
a read-out circuit section that reads out electric charge from the pixel section; and
a control circuit section that performs control to output pixel signals based on the read-out electric charge, wherein
the read-out circuit section includes the data transfer circuit according to claim 1 .
11. An imaging circuit device, comprising:
a pixel section in which a light-receiving element is disposed in each of a plurality of pixels;
a read-out circuit section that reads out electric charge from the pixel section; and
a control circuit section that performs control to output pixel signals based on the read-out electric charge, wherein
the read-out circuit section includes the data transfer circuit according to claim 2 .
12. An imaging circuit device, comprising:
a pixel section in which a light-receiving element is disposed in each of a plurality of pixels;
a read-out circuit section that reads out electric charge from the pixel section; and
a control circuit section that performs control to output pixel signals based on the read-out electric charge, wherein
the read-out circuit section includes the data transfer circuit according to claim 3 .
13. An imaging circuit device, comprising:
a pixel section in which a light-receiving element is disposed in each of a plurality of pixels;
a read-out circuit section that reads out electric charge from the pixel section; and
a control circuit section that performs control to output pixel signals based on the read-out electric charge, wherein
the read-out circuit section includes the data transfer circuit according to claim 4 .
14. An imaging circuit device, comprising:
a pixel section in which a light-receiving element is disposed in each of a plurality of pixels;
a read-out circuit section that reads out electric charge from the pixel section; and
a control circuit section that performs control to output pixel signals based on the read-out electric charge, wherein
the read-out circuit section includes the data transfer circuit according to claim 5 .
15. An imaging circuit device, comprising:
a pixel section in which a light-receiving element is disposed in each of a plurality of pixels;
a read-out circuit section that reads out electric charge from the pixel section; and
a control circuit section that performs control to output pixel signals based on the read-out electric charge, wherein
the read-out circuit section includes the data transfer circuit according to claim 6 .
16. An imaging circuit device, comprising:
a pixel section in which a light-receiving element is disposed in each of a plurality of pixels;
a read-out circuit section that reads out electric charge from the pixel section; and
a control circuit section that performs control to output pixel signals based on the read-out electric charge, wherein
the read-out circuit section includes the data transfer circuit according to claim 7 .
17. An imaging circuit device, comprising:
a pixel section in which a light-receiving element is disposed in each of a plurality of pixels;
a read-out circuit section that reads out electric charge from the pixel section; and
a control circuit section that performs control to output pixel signals based on the read-out electric charge, wherein
the read-out circuit section includes the data transfer circuit according to claim 8 .
18. An imaging circuit device, comprising:
a pixel section in which a light-receiving element is disposed in each of a plurality of pixels;
a read-out circuit section that reads out electric charge from the pixel section; and
a control circuit section that performs control to output pixel signals based on the read-out electric charge, wherein
the read-out circuit section includes the data transfer circuit according to claim 9 .
19. An electronic apparatus comprising one imaging circuit device according to claim 10 .
20. An electronic apparatus comprising a plurality of imaging circuit devices according to claim 10 that are connected in series.