Power-on reset circuit and under-voltage lockout circuit comprising the same

1. An under-voltage lockout (UVLO) circuit comprising:

a power-on reset (POR) circuit configured to generate an output based on a first current that flows according to an increase of a power supply voltage and not to operate in a normal state of the power supply voltage; and

a logic operation unit configured to generate a reset signal according to the output of the POR circuit and an output based on a result of a comparison between a sense voltage corresponding to the power supply voltage and a predetermined reference voltage,

wherein the POR circuit comprises:

a capacitor configured to be charged by the first current;

a current mirror configured to mirror the first current to a second current; and

a transistor configured to be operated by the second current.

2. The UVLO circuit of claim 1 , wherein the current mirror comprises:

a first current mirror configured to mirror the first current to a third current; and

a second current mirror configured to mirror the third current to the second current.

3. The UVLO circuit of claim 2 , wherein the first current mirror comprises:

a first transistor including a source coupled to the power supply voltage, a drain, and a gate, the drain and the gate being diode-connected; and

a second transistor including a gate coupled to the gate of the first transistor, a source coupled to the power supply voltage, and a drain coupled to the second current mirror,

wherein the capacitor is coupled to the drain of the first transistor.

4. The UVLO circuit of claim 3 , wherein the second current mirror comprises:

a third transistor including a drain coupled to the drain of the second transistor and a gate coupled to the drain thereof; and

a fourth transistor including a gate coupled to the gate of the third transistor and a drain coupled to a gate of the transistor.

5. The UVLO circuit of claim 1 , wherein the POR circuit further comprises:

a resistor coupled between the power supply voltage and the capacitor; and

a first transistor including a gate coupled to a node where the resistor and the capacitor are coupled and a source coupled to the power supply voltage,

wherein the current mirror is coupled to a drain of the first transistor.

6. The UVLO circuit of claim 5 , wherein the current mirror comprises:

a second transistor including a drain coupled to the drain of the first transistor and a gate coupled to the drain thereof; and

a third transistor including a gate coupled to the gate of the second transistor and a drain coupled to a gate of the transistor.

7. The UVLO circuit of claim 1 , wherein the POR circuit further comprises:

a first transistor configured to be turned on according to a predetermined first voltage and configured to block mirroring of the first current; and

a second transistor configured to be turned on according to a predetermined second voltage and to turn off the transistor.

8. The UVLO circuit of claim 7 , wherein the current mirror comprises two transistors mirroring a third current corresponding to the first current to the second current, and the first transistor is coupled between gates of the two transistors, and the predetermined first voltage is input to a gate of the first transistor.

9. The UVLO circuit of claim 7 , wherein the second transistor comprises a gate to which the predetermined second voltage is input, a first terminal coupled to the power supply voltage, and a second terminal coupled to a gate of the transistor.

10. The UVLO circuit of claim 7 , wherein the predetermined first voltage is the predetermined reference voltage compared with the sense voltage that corresponds to the power supply voltage for determination of the normal state of the power supply voltage, and the predetermined second voltage is the sense voltage.