Semiconductor device, semiconductor system, and system
View Patent ↗A semiconductor device, semiconductor system, and system may be provided. The semiconductor system may include one semiconductor device of a first semiconductor device and a second semiconductor device suitable for transmitting and receiving addresses and encrypted data. The one semiconductor device may include an address output circuit configured to output the addresses. The one semiconductor device may include an encryption circuit configured to output the encrypted data based on normal data and the addresses. The one semiconductor device may include a decryption circuit configured to output the normal data based on the addresses and the encrypted data.
1. A semiconductor system, comprises:
a controller; and
a memory device configured to receive mapping addresses and encrypted data from the controller, store the encrypted data in a location specified by the mapping address and, transmit stored encrypted data to the controller,
wherein the controller includes:
an address output circuit configured to output the mapping addresses;
an encryption circuit configured to receive normal data and output the encrypted data based on normal data by using the mapping addresses provided from the address output circuit; and
a decryption circuit configured to receive the stored encrypted data from the memory device and output the normal data by executing the stored encrypted data in response to the mapping addresses.
2. The semiconductor system according to claim 1 , wherein the encryption circuit performs a logic operation with the normal data and the addresses, and outputs the encrypted data.
3. The semiconductor system according to claim 2 , wherein the encryption circuit comprises a plurality of logic combining circuits which logically combine the normal data and the addresses.
4. The semiconductor system according to claim 3 , wherein each logic combining circuit outputs encrypted data of a first level when normal data and an address are the same level, and outputs encrypted data of a second level when normal data and an address are different levels, wherein the first level is a level different from the second level.
5. The semiconductor system according to claim 1 , wherein the decryption circuit performs a logic operation with the encrypted data and the addresses, and outputs the normal data.
6. The semiconductor system according to claim 5 , wherein the decryption circuit comprises a plurality of logic combining circuits which logically combine the encrypted data and the addresses.
7. The semiconductor system according to claim 6 , wherein each logic combining circuit outputs normal data of a first level when encrypted data and an address are the same level, and outputs normal data of a second level when encrypted data and an address are different levels, wherein the first level is a level different from the second level.