IP Library › Granted Patent US 9,563,384
Granted Patent B2
US 9,563,384 · App. 15/206,827 · Granted Feb 7, 2017

Systems and methods for data alignment in a memory system

Inventors: Stuart Allen Berke (Austin, TX); Bhyrav M. Mutnury (Round Rock, TX); Vadhiraj Sankaranarayanan (Austin, TX)
Assignee: Dell Products L.P.
G06F3/0659G06F3/0611G06F3/0635G06F3/0653G06F3/0683
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Quick Facts
Patent No.
US 9,563,384
App. No.
15/206,827
Granted
Feb 7, 2017
Kind
B2
Abstract

A method may include link training a plurality of back-side lanes coupling a plurality of memory chips of a memory module to a plurality of data buffers of the memory module. The method may also include link training a plurality of front-side lanes coupling the plurality of data buffers to a memory controller. The method may further include determining after link training of the back-side and front-side lanes whether signal integrity of data communicated over the front-side lanes exceeds one or more thresholds. The method may additionally include responsive to determining that the signal integrity of data communicated over one or more of the front-side lanes fails to exceed the one or more thresholds, modifying timing of data communicated over one or more of the back-side and front-side lanes in order to improve signal integrity of the one or more of the front-side lanes failing to exceed the thresholds.

Claims (43)

1. A system comprising:

a first device; and

a second device communicatively coupled to the first device; and

a plurality of buffers communicatively coupled to the second device via a plurality of back-side lanes and communicatively coupled to the first device via a plurality of front-side lanes;

wherein at least one of the first device and the second device is configured to, alone or in concert with the other:

link train the back-side lanes;

link train the front-side lanes;

determine after link training of the back-side lanes and the front-side lanes whether signal integrity of data communicated over each of the front-side lanes exceeds one or more thresholds; and

responsive to determining that the signal integrity of data communicated over one or more of the front-side lanes fails to exceed the one or more thresholds, modify timing of data communicated over one or more of the back-side lanes and the front-side lanes in order to improve signal integrity of the one or more of the front-side lanes failing to exceed the one or more thresholds.

2. The system of claim 1 , wherein at least one of the first device and the second device is further configured to, alone or in concert with the other:

identify one or more aggressor lanes for the one or more front-side lanes failing to exceed the one or more thresholds; and

modify timing of data in the one or more aggressor lanes in order to improve signal integrity of one or more of the one or more front-side lanes failing to exceed the one or more thresholds.

3. The system of claim 1 , wherein the second device is coupled to the first device via a multi-drop bus.

4. The system of claim 1 , wherein a bit width of the front-side lanes is greater than a bit width of the back-side lanes.

5. The system of claim 4 , wherein the bit width of the front-side lanes is twice than the bit width of the back-side lanes.

6. A method comprising:

link training a plurality of back-side lanes communicatively coupling a first device to a memory module to a plurality of data buffers integral to the memory module;

link training a plurality of front-side lanes communicatively coupling the plurality of data buffers to a second device;

determining after link training of the back-side lanes and the front-side lanes whether signal integrity of data communicated over each of the front-side lanes exceeds one or more thresholds; and

responsive to determining that the signal integrity of data communicated over one or more of the front-side lanes fails to exceed the one or more thresholds, modifying timing of data communicated over one or more of the back-side lanes and the front-side lanes in order to improve signal integrity of the one or more of the front-side lanes failing to exceed the one or more thresholds.

7. The method of claim 6 , further comprising:

identifying one or more aggressor lanes for the one or more front-side lanes failing to exceed the one or more thresholds; and

modifying timing of data in the one or more aggressor lanes in order to improve signal integrity of one or more of the one or more front-side lanes failing to exceed the one or more thresholds.

8. The method of claim 6 , wherein the first device is coupled to the second device via a multi-drop bus.

9. The method of claim 6 , wherein a bit width of the front-side lanes is greater than a bit width of the back-side lanes.

10. The method of claim 9 , wherein the bit width of the front-side lanes is twice than the bit width of the back-side lanes.

11. An information handing system, comprising:

a processor; and

a system comprising:

a first device; and

a second device communicatively coupled to the first device; and

a plurality of buffers communicatively coupled to the second device via a plurality of back-side lanes and communicatively coupled to the first device via a plurality of front-side lanes;

wherein at least one of the first device and the second device is configured to, alone or in concert with the other:

link train the back-side lanes;

link train the front-side lanes;

determine after link training of the back-side lanes and the front-side lanes whether signal integrity of data communicated over each of the front-side lanes exceeds one or more thresholds; and

responsive to determining that the signal integrity of data communicated over one or more of the front-side lanes fails to exceed the one or more thresholds, modify timing of data communicated over one or more of the back-side lanes and the front-side lanes in order to improve signal integrity of the one or more of the front-side lanes failing to exceed the one or more thresholds.

12. The information handling system of claim 11 , wherein at least one of the first device and the second device is further configured to, alone or in concert with the other:

identify one or more aggressor lanes for the one or more front-side lanes failing to exceed the one or more thresholds; and

modify timing of data in the one or more aggressor lanes in order to improve signal integrity of one or more of the one or more front-side lanes failing to exceed the one or more thresholds.

13. The information handling system of claim 11 , wherein the first device is coupled to the second device via a multi-drop bus.

14. The information handling system of claim 11 , wherein a bit width of the front-side lanes is greater than a bit width of the back-side lanes.

15. The information handling system of claim 11 , wherein the bit width of the front-side lanes is twice than the bit width of the back-side lanes.

Assignments (14)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (042769/0001) Recorded Apr 26, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MOZY, INC.); DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO WYSE TECHNOLOGY L.L.C.)
Reel/Frame 059803/0802 →
RELEASE OF SECURITY INTEREST AT REEL 042768 FRAME 0585 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; MOZY, INC.; WYSE TECHNOLOGY L.L.C.
Reel/Frame 058297/0536 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
PATENT SECURITY INTEREST (CREDIT) Recorded Jun 12, 2017
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; MOZY, INC.; WYSE TECHNOLOGY L.L.C.
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 042768/0585 →
PATENT SECURITY INTEREST (NOTES) Recorded Jun 12, 2017
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; MOZY, INC.; WYSE TECHNOLOGY L.L.C.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 042769/0001 →
RELEASE OF SEC. INT. IN PATENTS (TL) Recorded Sep 14, 2016
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVENTAIL LLC; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.
Reel/Frame 040027/0329 →
RELEASE OF SEC. INT. IN PATENTS (NOTES) Recorded Sep 14, 2016
From: BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
To: AVENTAIL LLC; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.
Reel/Frame 040026/0710 →
RELEASE OF SEC. INT. IN PATENTS (ABL) Recorded Sep 13, 2016
From: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
To: AVENTAIL LLC; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.
Reel/Frame 040013/0733 →
SUPPLEMENT TO PATENT SECURITY AGREEMENT (TERM LOAN) Recorded Aug 10, 2016
From: AVENTAIL LLC; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 039719/0889 →
SUPPLEMENT TO PATENT SECURITY AGREEMENT (NOTES) Recorded Aug 10, 2016
From: AVENTAIL LLC; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 039644/0084 →
SUPPLEMENT TO PATENT SECURITY AGREEMENT (ABL) Recorded Aug 10, 2016
From: AVENTAIL LLC; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.
To: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 039643/0953 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 11, 2016
From: BERKE, STUART ALLEN; MUTNURY, BHYRAV M.; SANKARANARAYANAN, VADHIRAJ
To: DELL PRODUCTS L.P.
Reel/Frame 039124/0001 →
Continuity (2)
Continuation 14667356 · Mar 24, 2015
Related Publication 20160321014A1 · Nov 3, 2016