IP Library Granted Patent US 10,048,894
Granted Patent B2
US 10,048,894 · App. 15/208,520 · Granted Aug 14, 2018

Reducing cache memory requirements for recording statistics from testing with a multiplicity of flows

Inventors: Jocelyn Kunimitsu (Aiea, HI); Craig Fujikami (Honolulu, HI)
Assignee: Spirent Communications, Inc.
G06F3/0656G06F3/0604G06F3/067G06F3/0622G06F12/0802G06F2212/60
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Quick Facts
Patent No.
US 10,048,894
App. No.
15/208,520
Granted
Aug 14, 2018
Kind
B2
Abstract

A disclosed method processes a data feed including multiple streams. The method includes processing n frames of the multiple streams in parallel through n processing pipelines, n being an integer greater than or equal to 2. The n frames include a first frame belonging to a first stream and a second frame belonging to a second stream. The first stream is different than the second stream. The n processing pipelines are coupled to n-by-n value buffers per stream per recorded value for the stream, and at least one status buffer per stream. The n processing pipelines are each assigned a distinct row of read-authorized port access to the n-by-n value buffers and a distinct column of write-authorized port access to the n-by-n value buffers.

Claims (95)

1. A method of processing a data feed including multiple streams, comprising:

processing n frames of the multiple streams in parallel through n processing pipelines, n being an integer greater than or equal to 2, the n frames including a first frame belonging to a first stream and a second frame belonging to a second stream, wherein the first stream is different than the second stream, the n processing pipelines being coupled to:

n-by-n value buffers per stream per recorded value for the stream; and

at least one status buffer per stream;

wherein the n processing pipelines are each assigned a distinct row of read-authorized port access to the n-by-n value buffers and a distinct column of write-authorized port access to the n-by-n value buffers; and

in a first processing pipeline:

reading, for the first stream, a first row of the n-by-n value buffers using the read-authorized port to the value buffers in the first row;

reading a first status buffer to determine which of the value buffers in the first row contains a most recently updated value and processing the most recently updated value to produce a currently updated value; and

writing the currently updated value to a first column of the n-by-n value buffers using the write-authorized port, while writing to the first status buffer to indicate that the first column of the value buffers has been updated with the most recently updated value, more recently than a second column of the value buffers.

2. The method of claim 1 , wherein in a second processing pipeline:

reading, for the second stream, a second row of the n-by-n value buffers using the read-authorized port to the value buffers in the row;

reading a second status buffer to determine which of the value buffers in the second row contains a most recently updated value and processing the most recently updated value to produce a currently updated value; and

writing the currently updated value to a second column of the n-by-n value buffers using the write-authorized port, while writing to the status buffer to indicate that the second column of the value buffers has been updated with the most recently updated value.

3. The method of claim 1 , further comprising:

repeatedly applying the method of claim 1 to at least hundreds of millions of frames per second from at least thousands of streams, each stream having one or more n-by-n value buffers and one or more status buffers.

4. The method of claim 2 , further comprising:

repeatedly applying the method of claim 2 to at least hundreds of millions of frames per second from at least thousands of streams, each stream having one or more n-by-n value buffers and one or more status buffers.

5. The method of claim 1 , further comprising:

identifying streams to which the n frames belong, and checking that all of the streams are different.

6. The method of claim 1 , further comprising:

identifying streams to which the n frames belong, and responsive to at least two of the streams being a same stream, merging the frames belonging to the same stream into a single frame.

7. The method of claim 1 , wherein

the recorded value is an order-based statistic for the first stream and at least two sets of n-by-n value buffers contain a most recent frame sequence value used to determine the order-based statistic and an order-based statistic counter used to store results of an order-based comparison.

8. The method of claim 1 , wherein

the n processing pipelines have a combined throughput of at least two frames per clock cycle of a clock for the n-by-n value buffers and the at least one status buffer.

9. The method of claim 1 , wherein

responsive to writing the currently updated value to rows of the first column of the n-by-n value buffers using the write-authorized port, the currently updated value is mirrored across the rows of the first column of the n-by-n value buffers.

10. The method of claim 1 , further comprising:

prior to the processing the n frames, generating the n frames of test traffic.

11. The method of claim 1 , further comprising:

prior to the processing the n frames, receiving the n frames of test traffic.

12. A computing device that processes a data feed including multiple streams, the computing device including a field-programmable gate array (FPGA), the FPGA configured to perform operations comprising:

processing n frames of the multiple streams in parallel through n processing pipelines, n being an integer greater than or equal to 2, the n frames including a first frame belonging to a first stream and a second frame belonging to a second stream, wherein the first stream is different than the second stream, the n processing pipelines being coupled to:

n-by-n value buffers per stream per recorded value for the stream; and

at least one status buffer per stream;

wherein the n processing pipelines are each assigned a distinct row of read-authorized port access to the n-by-n value buffers and a distinct column of write-authorized port access to the n-by-n value buffers; and

in a first processing pipeline:

reading, for the first stream, a first row of the n-by-n value buffers using the read-authorized port to the value buffers in the row;

reading a first status buffer to determine which of the value buffers in the first row contains a most recently updated value and processing the most recently updated value to produce a currently updated value; and

writing the currently updated value to a first column of the n-by-n value buffers using the write-authorized port, while writing to the first status buffer to indicate that the first column of the value buffers has been updated with the most recently updated value.

13. The computing device of claim 12 , wherein the FPGA is configured to perform the operations further comprising:

in a second processing pipeline:

reading, for the second stream, a second row of the n-by-n value buffers using the read-authorized port to the value buffers in the row;

reading a second status buffer to determine which of the value buffers in the second row contains a most recently updated value and processing the most recently updated value to produce a currently updated value; and

writing the currently updated value to a second column of the n-by-n value buffers using the write-authorized port, while writing to the status buffer to indicate that the second column of the value buffers has been updated with the most recently updated value.

14. The computing device of claim 12 , wherein the FPGA is configured to perform the operations further comprising:

repeatedly applying the operations of claim 12 to at least hundreds of millions of frames per second from at least thousands of streams, each stream having one or more n-by-n value buffers and one or more status buffers.

15. The computing device of claim 13 , wherein the FPGA is configured to perform the operations further comprising:

repeatedly applying the operations of claim 13 to at least hundreds of millions of frames per second from at least thousands of streams, each stream having one or more n-by-n value buffers and one or more status buffers.

16. The computing device of claim 12 , wherein the FPGA is configured to perform the operations further comprising:

identifying streams to which the n frames belong, and checking that all of the streams are different.

17. The computing device of claim 12 , wherein the FPGA is configured to perform the operations further comprising:

identifying streams to which the n frames belong, and responsive to at least two of the streams being a same stream, merging the frames belonging to the same stream into a single frame.

18. The computing device of claim 12 , wherein the FPGA is configured such that:

the recorded value is an order-based statistic for the first stream and at least two sets of n-by-n value buffers contain a most recent frame sequence value used to determine the order-based statistic and an order-based statistic counter used to store results of an order-based comparison.

19. The computing device of claim 12 , wherein the FPGA is configured such that:

the n processing pipelines have a combined throughput of at least two frames per clock cycle of a clock for the n-by-n value buffers and the at least one status buffer.

20. The computing device of claim 12 , wherein the FPGA is configured such that:

responsive to writing the currently updated value to rows of the first column of the n-by-n value buffers using the write-authorized port, the currently updated value is mirrored across the rows of the first column of the n-by-n value buffers.

21. The computing device of claim 12 , wherein the FPGA is configured the operations further comprising:

prior to the processing the n frames, generating the n frames of test traffic.

22. The computing device of claim 12 , wherein the FPGA is configured the operations further comprising:

prior to the processing the n frames, receiving the n frames of test traffic.

23. A nontransitory computer readable medium storing a field-programmable gate array (FPGA) configuration that processes a data feed including multiple streams, which when loaded into an FPGA configures the FPGA to perform operations comprising:

processing n frames of the multiple streams in parallel through n processing pipelines, n being an integer greater than or equal to 2, the n frames including a first frame belonging to a first stream and a second frame belonging to a second stream, wherein the first stream is different than the second stream, the n processing pipelines being coupled to:

n-by-n value buffers per stream per recorded value for the stream; and

at least one status buffer per stream;

wherein the n processing pipelines are each assigned a distinct row of read-authorized port access to the n-by-n value buffers and a distinct column of write-authorized port access to the n-by-n value buffers; and

in a first processing pipeline:

reading, for the first stream, a first row of the n-by-n value buffers using the read-authorized port to the value buffers in the row;

reading a first status buffer to determine which of the value buffers in the first row contains a most recently updated value and processing the most recently updated value to produce a currently updated value; and

writing the currently updated value to a first column of the n-by-n value buffers using the write-authorized port, while writing to the first status buffer to indicate that the first column of the value buffers has been updated with the most recently updated value.

24. The nontransitory computer readable medium of claim 23 , wherein the FPGA configuration configures the FPGA to perform the operations further comprising:

in a second processing pipeline:

reading, for the second stream, a second row of the n-by-n value buffers using the read-authorized port to the value buffers in the row;

reading a second status buffer to determine which of the value buffers in the second row contains a most recently updated value and processing the most recently updated value to produce a currently updated value; and

writing the currently updated value to a second column of the n-by-n value buffers using the write-authorized port, while writing to the status buffer to indicate that the second column of the value buffers has been updated with the most recently updated value.

25. The nontransitory computer readable medium of claim 23 , wherein the FPGA configuration configures the FPGA to perform the operations further comprising:

repeatedly applying the operations of claim 23 to at least hundreds of millions of frames per second from at least thousands of streams, each stream having one or more n-by-n value buffers and one or more status buffers.

26. The nontransitory computer readable medium of claim 24 , wherein the FPGA configuration configures the FPGA further comprising:

repeatedly applying the operations of claim 24 to at least hundreds of millions of frames per second from at least thousands of streams, each stream having one or more n-by-n value buffers and one or more status buffers.

27. The nontransitory computer readable medium of claim 23 , wherein the FPGA configuration configures the FPGA to perform the operations further comprising:

identifying streams to which the n frames belong, and checking that all of the streams are different.

28. The nontransitory computer readable medium of claim 23 , wherein the FPGA configuration configures the FPGA to perform the operations further comprising:

identifying streams to which the n frames belong, and responsive to at least two of the streams being a same stream, merging the frames belonging to the same stream into a single frame.

29. The nontransitory computer readable medium of claim 23 , wherein the FPGA configuration configures the FPGA such that:

the recorded value is an order-based statistic for the first stream and at least two sets of n-by-n value buffers contain a most recent frame sequence value used to determine the order-based statistic and an order-based statistic counter used to store results of an order-based comparison.

30. The nontransitory computer readable medium of claim 23 , wherein the FPGA configuration configures the FPGA such that:

the n processing pipelines have a combined throughput of n frames per clock cycle of a clock for the n-by-n value buffers and the at least one status buffer.

31. The nontransitory computer readable medium of claim 23 , wherein the FPGA configuration configures the FPGA such that:

responsive to writing the currently updated value to rows of the first column of the n-by-n value buffers using the write-authorized port, the currently updated value is mirrored across the rows of the first column of the n-by-n value buffers.

32. The nontransitory computer readable medium of claim 23 , wherein the FPGA configuration configures the FPGA such that:

prior to the processing the n frames, generating the n frames of test traffic.

33. The nontransitory computer readable medium of claim 23 , wherein the FPGA configuration configures the FPGA such that:

prior to the processing the n frames, receiving the n frames of test traffic.

Assignments (5)
RELEASE OF SECURITY INTEREST AT REEL/FRAME 73189/0873 Recorded May 28, 2026
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
To: INERTIAL LABS, INC.; VIAVI SOLUTIONS INC.; VIAVI SOLUTIONS LICENSING LLC
Reel/Frame 075642/0381 →
SECURITY INTEREST Recorded Nov 14, 2025
From: VIAVI SOLUTIONS INC.; VIAVI SOLUTIONS LICENSING LLC; INERTIAL LABS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS AGENT
Reel/Frame 073571/0137 →
SECURITY AGREEMENT Recorded Oct 21, 2025
From: INERTIAL LABS, INC.; VIAVI SOLUTIONS INC.; VIAVI SOLUTIONS LICENSING LLC
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 073189/0873 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 20, 2025
From: SPIRENT COMMUNICATIONS, INC.
To: VIAVI SOLUTIONS LICENSING LLC
Reel/Frame 073121/0549 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2016
From: KUNIMITSU, JOCELYN; FUJIKAMI, CRAIG
To: SPIRENT COMMUNICATIONS, INC
Reel/Frame 039171/0042 →
Continuity (1)
Related Publication 20180018130A1 · Jan 18, 2018