Integrated photo detector, method of making the same

1. An integrated photo detector with enhanced electrostatic discharge damage (ESD) protection comprising:

an input waveguide formed in a Si-on-insulator (SOI) substrate for receiving a light wave;

a first photodiode formed in the SOI substrate and coupled to the input waveguide, the first photodiode being associated with a first p-electrode and a first n-electrode;

a second photodiode formed in the SOI substrate associated with a second p-electrode and a second n-electrode forming a capacitance no larger than a few femto Faradays;

a first electrode and a second electrode disposed respectively on the SOI substrate, the first/second electrode being respectively connected to the first p/n-electrode via a first/second metallic layer patterned with a reduced width from the first/second electrode to the first p/n-electrode and connected to the second p/n-electrode via a first/second metallic wire.

2. The integrated photo detector of claim 1 , wherein the first photodiode is a Germanium-based photodiode configured to detect the light wave modulated with a high data rate.

3. The integrated photo detector of claim 1 , wherein the input waveguide comprise a material of silicon or germanium or silicon nitride formed in the SOI substrate for transmitting the light wave therein.

4. The integrated photo detector of claim 2 , wherein the Germanium-based photodiode comprises a p-type Silicon base patterned within the SOI substrate and an intrinsic Germanium block formed overlying the p-type Silicon base, the p-type Silicon base being partially implanted via a first mask to form a first p++ doped region and the intrinsic Germanium block being partially implanted via a second mask to form a first n++ doped region.

5. The integrated photo detector of claim 4 , wherein the first p-electrode is physically bounded onto the p++ doped region and the first n-electrode is physically bounded onto the n++ doped region.

6. The integrated photo detector of claim 1 , wherein the second photodiode is a Silicon-based photodiode coupled to the Germanium-based photodiode to provide an electrostatic discharge damage threshold of ±100V or higher.

7. The integrated photo detector of claim 6 , wherein the Silicon-based photodiode comprises a p-type Silicon region joined with an n-type Silicon region patterned within the SOI substrate, the p-type Silicon region being partially implanted via a third mask to form a second p++ doped region and the n-type Silicon region being partially implanted via a fourth mask to form a second n++ doped region.

8. The integrated photo detector of claim 1 , wherein each of the second p-electrode and the second n-electrode is made substantially smaller in size than each of the first p-electrode and the first n-electrode.

9. The integrated photo detector of claim 2 , wherein each of the first electrode and the second electrode is made substantially larger in size up to a few tens to hundreds of micrometers sufficient for forming a soldering connection with an external digital circuit for outputting an electric signal converted by the Germanium-based photodiode.

10. The integrated photo detector of claim 9 wherein the electric signal substantially maintains the high data rate of the light wave.

11. The integrated photo detector of claim 1 , wherein the first/second p/n-electrode, the first/second electrode, the first/second metallic layer, and the first/second metallic wire are substantially made from a single metallic layer via a unified patterning process.

12. The integrated photo detector of claim 1 , wherein the first/second metallic wire comprises a substantially thin trace line of a few micrometers or less for minimizing the capacitance and sufficient to maintain electrical connection between the first/second electrode and the second p-type/n-type region.

13. An integrated photo detector with enhanced electrostatic discharge damage (ESD) protection comprising:

a Germanium photodiode comprising an intrinsic Germanium layer formed on a p-type Silicon base layer patterned within a Si-on-Insulator (SOI) substrate, the intrinsic Germanium layer comprising a first n++ doped region and the p-type Silicon base layer comprising a first p++ doped region;

a Silicon photodiode comprising a Silicon region patterned within the SOI substrate to form a p-type Silicon portion joined with a n-type Silicon portion, the p-type Silicon portion comprising a second p++ doped region and the n-type Silicon portion comprising a second n++ doped region;

a first metallic layer being pattered to include a first p-electrode coupled to the first p++ doped region, a second p-electrode coupled to the second p++ doped region, a first electrode connected to the first p-electrode by a portion of the first metallic layer with a reducing width and connected to the second p-electrode by a first trace line;

a second metallic layer being pattered to include a first n-electrode coupled to the first n++ doped region, a second n-electrode coupled to the second n++ doped region, a second electrode connected to the first n-electrode by a portion of the second metallic layer with a reducing width and connected to the second n-electrode by a second trace line;

wherein the Silicon photodiode is coupled with the Germanium photodiode electrically in parallel with a capacitance of no greater than a few femto Faradays and an enhanced ESD threshold of about ±100V.

14. A method for manufacturing an integrated photo detector with improved electrostatic discharge damage (ESD) protection, the method comprising:

forming a first Silicon base block and a second Silicon base block on a substrate;

forming a Germanium photodiode partially in the first Silicon base block, the Germanium photodiode being associated with a first p-electrode and a first n-electrode;

forming a Silicon photodiode in the second Silicon bask block, the Silicon photodiode being associated with a second p-electrode and a second n-electrode, the second p-electrode and the second n-electrode serving as two terminals of a capacitance no larger than a few femto Faradays;

forming a first electrode and a second electrode separately on the substrate;

forming a first metallic layer on the substrate, the first metallic layer being patterned to have a first portion with a reducing width connecting the first electrode to the first p-electrode and a second portion with a first trace line connecting the first electrode to the second p-electrode;

forming a second metallic layer on the substrate, the second metallic layer being patterned to have a third portion with a reducing width to connect the second electrode to the first n-electrode and a fourth portion with a second trace line to connect the second electrode to the second n-electrode.

15. The method of claim 14 wherein the first Silicon base block is a p-type Silicon layer and the second Silicon base block comprises a p-type Silicon portion joined with a n-type Silicon portion.

16. The method of claim 15 wherein forming the Germanium photodiode comprises depositing an intrinsic Germanium layer on the p-type Silicon layer of the first Silicon base block; implanting a first n++ doped region in the intrinsic Germanium layer by masked implantation; implanting a first p++ doped region in the p-type Silicon layer; coupling the first n++ doped region to the first n-electrode; and coupling the first p++ region to the first p-electrode.

17. The method of claim 15 wherein forming the Silicon photodiode comprises implanting a second p++ doped region in the p-type Silicon portion of the second Silicon base block; implanting a second n++ doped region in the n-type Silicon portion of the second Silicon base block; coupling the second p++ doped region to the second p-electrode; and

coupling the second n++ doped region to the second n-electrode.

18. The method of claim 14 wherein the first/second metallic layer is configured to couple the Silicon photodiode to the Germanium photodiode electrically in parallel with a characterized ESD threshold of about ±100V.

19. The method of claim 18 further comprising forming an input waveguide on the substrate to couple with the Germanium photodiode for receiving a light wave modulated with a high data rate.

20. The method of claim 19 wherein the first/second electrode comprises a dimension of a few tens to hundreds of micrometers sufficient for forming a solder bump to connect with an external electronic circuit and output an electric signal generated by the Germanium photodiode by detecting the light wave received from the input waveguide.

21. The method of claim 20 wherein the electric signal substantially maintains the high data rate of the light wave depended on modulation.

22. The method of claim 14 wherein the first/second trace line comprises a width of a few micrometers or less to minimize its parasitic capacitance.

23. The method of claim 14 wherein the substrate is a silicon-on-insulator substrate.