Semiconductor memory device
View Patent ↗A semiconductor memory device includes a conductive layer on a source side; a first electrode layer provided on the conductive layer; a second electrode layer provided between the conductive layer and the first electrode layer; a semiconductor layer extending through the first electrode in a first direction from the conductive layer to the first electrode layer; a first semiconductor body provided between the conductive layer and the semiconductor layer, the first semiconductor body including first impurities; and a second semiconductor body provided between the conductive layer and the first semiconductor body, the second semiconductor body including second impurities with a higher concentration than a concentration of the first impurities in the first semiconductor body. A diffusion coefficient of the second impurities in the second semiconductor body is smaller than a diffusion coefficient of the second impurities in the first semiconductor body.
1. A semiconductor memory device comprising:
a conductive layer on a source side;
a first electrode layer provided above the conductive layer;
a second electrode layer provided between the conductive layer and the first electrode layer;
a semiconductor layer extending through the first electrode layer in a first direction from the conductive layer to the first electrode layer;
a first semiconductor body provided between the conductive layer and the semiconductor layer, the first semiconductor body including first impurities; and
a second semiconductor body provided between the conductive layer and the first semiconductor body, the second semiconductor body including a first potion and a second portion, the first portion being positioned between the conductive layer and the first semiconductor body, and the second portion being positioned between the first portion and the first semiconductor body,
the second semiconductor body including second impurities with a higher concentration than a concentration of the first impurities in the first semiconductor body,
the second portion includes a part of the second impurities with a lower concentration than a concentration of another part of the second impurities in the first portion and with a higher concentration than a concentration of the first impurities in the first semiconductor body, and
a diffusion coefficient of the second impurities in the second semiconductor body being smaller than a diffusion coefficient of the first impurities in the first semiconductor body.
2. The semiconductor memory device according to claim 1 , wherein
the first semiconductor body extends in the first direction through the second electrode layer.
3. The semiconductor memory device according to claim 2 , wherein
the first semiconductor body has one end positioned at a level between the conductive layer and the second electrode layer, and another end positioned at a level between the first electrode layer and the second electrode layer.
4. The semiconductor memory device according to claim 1 , wherein
the second semiconductor body has one end positioned at a level between the conductive layer and the second electrode layer, and another end positioned in the conductive layer.
5. The semiconductor memory device according to claim 4 , wherein
the first semiconductor body covers the one end of the second semiconductor body.
6. The semiconductor memory device according to claim 1 , wherein
the second semiconductor body is electrically connected to the conductive layer.
7. The semiconductor memory device according to claim 1 , wherein
the semiconductor layer has a poly-crystalline structure, and
the first and second semiconductor bodies have a single-crystalline structure.
8. The semiconductor memory device according to claim 1 , further comprising:
a plurality of first electrode layers stacked in the first direction,
wherein the semiconductor layer extends in the first direction through the first electrode layers.
9. The semiconductor memory device according to claim 1 , further comprising:
a memory cell including a charge storage portion provided between the first electrode layer and the semiconductor layer.
10. The semiconductor memory device according to claim 1 , wherein
the first electrode layer and the second electrode layer each include metal.
11. The semiconductor memory device according to claim 1 , wherein the first semiconductor body includes no intentionally doped impurity.
12. A semiconductor memory device comprising:
a conductive layer on a source side;
a first electrode layer provided above a conductive layer;
a second electrode layer provided between the conductive layer and the first electrode layer;
a semiconductor layer extending through the first electrode layer in a first direction from the conductive layer to the first electrode layer;
a first semiconductor body provided between the conductive layer and the semiconductor layer, and extending though the second electrode layer, the first semiconductor body including first impurities; and
a second semiconductor body provided between the conductive layer and the first semiconductor body, the second semiconductor body including second impurities with higher concentration than a concentration of the first impurities in the first semiconductor body,
the first semiconductor body and the second semiconductor body each including silicon as a main constituent;
the second semiconductor body further including at least one of germanium and carbon with a higher concentration in a portion positioned at a level of a surface of the conductive layer on the second electrode layer side than a concentration of the at least one of germanium and carbon in an end portion of the first semiconductor body on the semiconductor layer side.
13. The semiconductor memory device according to claim 12 , wherein
the semiconductor layer is a poly-crystalline silicon layer, and
the first and second semiconductor bodies are single-crystalline silicon layers.
14. The semiconductor memory device according to claim 12 , wherein
the second impurities are at least one of boron, arsenic and phosphorus.
15. The semiconductor memory device according to claim 12 , further comprising:
a silicon oxide layer provided between the second electrode layer and the first semiconductor body.
16. The semiconductor memory device according to claim 12 , wherein
the second semiconductor body has one end positioned at a level between the conductive layer and the second electrode layer, and another end positioned in the conductive layer.
17. The semiconductor memory device according to claim 12 , wherein
the second semiconductor body is electrically connected to the conductive layer.
18. The semiconductor memory device according to claim 12 , further comprising:
a plurality of first electrode layers stacked in the first direction,
wherein the semiconductor layer extends in the first direction through the first electrode layers.
19. The semiconductor memory device according to claim 12 , further comprising:
a memory cell including a charge storage portion provided between the first electrode layer and the semiconductor layer.
20. The semiconductor memory device according to claim 12 , wherein
the first electrode layer and the second electrode layer each include metal.
21. A semiconductor memory device comprising:
a conductive layer on a source side;
a first electrode layer provided above the conductive layer;
a second electrode layer provided between the conductive layer and the first electrode layer;
a semiconductor layer extending through the first electrode layer in a first direction from the conductive layer to the first electrode layer, the semiconductor layer having a poly-crystalline structure;
a first semiconductor body provided between the conductive layer and the semiconductor layer, the first semiconductor body having a single-crystalline structure, and including first impurities; and
a second semiconductor body provided between the conductive layer and the first semiconductor body, the second semiconductor body having a single-crystalline structure, and including second impurities with a higher concentration than a concentration of the first impurities in the first semiconductor body,
a diffusion coefficient of the second impurities in the second semiconductor body being smaller than a diffusion coefficient of the first impurities in the first semiconductor body.
22. The semiconductor memory device according to claim 21 , wherein
the first semiconductor body extends in the first direction through the second electrode layer.
23. The semiconductor memory device according to claim 22 , wherein
the first semiconductor body has one end positioned at a level between the conductive layer and the second electrode layer, and another end positioned at a level between the first electrode layer and the second electrode layer.
24. The semiconductor memory device according to claim 21 wherein
the second semiconductor body has one end positioned at a level between the conductive layer and the second electrode layer, and another end positioned in the conductive layer.
25. The semiconductor memory device according to claim 24 , wherein
the first semiconductor body covers the one end of the second semiconductor body.
26. The semiconductor memory device according to claim 21 , wherein the second semiconductor body is electrically connected to the conductive layer.
27. The semiconductor memory device according to claim 21 , wherein the first semiconductor body includes no intentionally doped impurity.