IP Library Granted Patent US 9,922,706
Granted Patent B2
US 9,922,706 · App. 15/215,913 · Granted Mar 20, 2018

Solid state storage device using state prediction method

Inventors: Shih-Jia Zeng (Taipei, TW); Jen-Chien Fu (Taipei, TW)
Assignees: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED; LITE-ON TECHNOLOGY CORPORATION
G11C11/5642G06F3/064G06F3/0611G06F3/0619G06F3/0652G06F3/0653G06F3/0679G06F11/1068G11C11/5628G11C16/0408G11C16/0483G11C16/10G11C16/26G11C29/52
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Quick Facts
Patent No.
US 9,922,706
App. No.
15/215,913
Granted
Mar 20, 2018
Kind
B2
Abstract

A solid state storage includes a non-volatile memory and a controlling circuit. The non-volatile memory includes a first block. The controlling circuit is connected with the non-volatile memory. The controlling circuit includes a function storage circuit. The function storage circuit stores plural prediction functions. According to plural state parameters corresponding to the first block and a first prediction function of the plural prediction functions, the controlling circuit predicts a read voltage shift of the first block.

Claims (23)

1. A solid state storage device, comprising:

a non-volatile memory comprising a first block; and

a controlling circuit connected with the non-volatile memory, wherein the controlling circuit comprises a function storage circuit, and the function storage circuit stores plural prediction functions,

wherein according to plural state parameters corresponding to the first block and a first prediction function of the plural prediction functions, the controlling circuit determines a read voltage shift of the first block,

wherein according to the plural state parameters corresponding to the first block and a second prediction function of the plural prediction functions, the controlling circuit determines that a second decoding process is suitable for the first block at a future time point.

2. The solid state storage device as claimed in claim 1 , wherein the plural state parameters include at least one of a block program time, a block program count, a block erase time, a block erase count, a block error bit number, a block read voltage, a block decoding process, a temperature, a block read count, a histogram parameter or a read voltage interval.

3. The solid state storage device as claimed in claim 1 , wherein according to the read voltage shift, the controlling circuit generates a read voltage to the first block of the non-volatile memory and acquires a read data of the first block according to the read voltage.

4. The solid state storage device as claimed in claim 3 , wherein according to the plural state parameters corresponding to the first block and a third prediction function of the plural prediction functions, the controlling circuit determines that a first decoding process is suitable for the first block.

5. The solid state storage device as claimed in claim 4 , wherein the controlling circuit further comprises an error correction circuit for performing the first decoding process and correcting plural error bits of the read data, thereby generating a corrected read data to a host.

6. The solid state storage device as claimed in claim 1 , wherein according to the plural state parameters corresponding to the first block and a fourth prediction function of the plural prediction functions, the controlling circuit determines the read voltage shift of the first block at a future time point.

7. The solid state storage device as claimed in claim 1 , wherein if the controlling circuit determines that the first block is not successfully decoded at the future time point according to the plural state parameters corresponding to the first block and the second prediction function, a data of the first block is stored into a second block by the controlling circuit.

8. The solid state storage device as claimed in claim 1 , wherein the plural prediction functions are previously stored in the function storage circuit before the solid state storage device leaves a factory.

9. A solid state storage device, comprising:

a non-volatile memory comprising a first block; and

a controlling circuit connected with the non-volatile memory, wherein the controlling circuit comprises a function storage circuit, and the function storage circuit stores plural prediction functions,

wherein according to plural state parameters corresponding to the first block and a first prediction function of the plural prediction functions, the controlling circuit determines a read voltage shift of the first block,

wherein after the plural state parameters corresponding to plural blocks of the non-volatile memory are collected, the plural state parameters are recorded in an information table of the non-volatile memory, wherein first portions of the plural state parameters are set as input terms, second portions of the plural state parameters are set as output terms, and the plural prediction functions are obtained according to a machine learning algorithm which is performed according to a linear regression method, a Lasso regression method, a Ridge regression method or support vector machine.

10. A solid state storage device, comprising:

a non-volatile memory comprising a first block; and

a controlling circuit connected with the non-volatile memory, wherein the controlling circuit comprises a function storage circuit, and the function storage circuit stores plural prediction functions,

wherein according to plural state parameters corresponding to the first block and a first prediction function of the plural prediction functions, the controlling circuit determines a read voltage shift of the first block,

wherein the plural prediction functions include plural future read voltage prediction functions for calculating a power-off period of the solid state storage device at plural future time points.

11. The solid state storage device as claimed in claim 10 , wherein before the solid state storage device is powered down, the plural state parameters of a reference blocks are stored, wherein when the solid state storage device is powered on again, the reference block is corrected and a read voltage shift of the reference block is obtained, wherein according to the read voltage shift, the controlling circuit determines a suitable read voltage prediction function and calculates a power-off period of the solid state storage device.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2019
From: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED; LITE-ON TECHNOLOGY CORPORATION
To: SOLID STATE STORAGE TECHNOLOGY CORPORATION
Reel/Frame 051213/0824 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 21, 2016
From: ZENG, SHIH-JIA; FU, JEN-CHIEN
To: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED; LITE-ON TECHNOLOGY CORPORATION
Reel/Frame 039210/0529 →
Priority Claims (1)
CN 2016 1 0378726 · May 31, 2016 · national
Continuity (1)
Related Publication 20170345489A1 · Nov 30, 2017