IP Library Granted Patent US 10,135,275
Granted Patent B2
US 10,135,275 · App. 15/219,248 · Granted Nov 20, 2018

Pulsed level shift and inverter circuits for GaN devices

Inventors: Daniel M. Kinzer (El Segundo, CA); Santosh Sharma (Laguna Nigel, CA); Ju Jason Zhang (Monterey Park, CA)
Assignee: NAVITAS SEMICONDUCTOR INC.
H02J7/0052H01L23/528H01L25/072H01L27/088H01L27/0883H01L29/1033H01L29/2003H01L29/402H01L29/41758H02M1/088H02M3/157H02M3/1584H02M3/1588H03K3/012H03K3/356017H03K17/102H03K19/018507H01L2924/00H01L2924/0002H02M3/155H02M2001/0048Y02B70/1466Y02B70/1483
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Quick Facts
Patent No.
US 10,135,275
App. No.
15/219,248
Granted
Nov 20, 2018
Kind
B2
Abstract

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.

Claims (12)

1. A level shift circuit, comprising:

a first inverter circuit comprising:

a first input terminal;

a first output terminal;

a first GaN-based transistor having a gate coupled to the first input terminal, a drain coupled to the first output terminal, and a source coupled to a ground; and

a first pull up device coupled between the drain of the first GaN-based transistor and a power supply, wherein the first pull up device is configured to selectively conduct current from the power supply to the output terminal, wherein the first pull up device comprises a second GaN-based transistor having a gate driven with a voltage based on the voltage at the first output terminal, and wherein the first and second GaN-based transistors are of the same conductivity type.

2. The circuit of claim 1 , wherein the power supply is a floating power supply.

3. The circuit of claim 1 , wherein the gate of the second GaN-based transistor is coupled to an output of a buffer circuit, and wherein an input of the buffer circuit is coupled to the first output terminal.

4. The circuit of claim 3 , wherein the buffer circuit is configured to generate a pulse in response to an input transition at the input of the buffer circuit.

5. The circuit of claim 1 , further comprising a second pull up device coupled between the drain of the first GaN-based transistor and the power supply.

6. The circuit of claim 5 , wherein the second pull up device conducts current passively.

7. The circuit of claim 5 , further comprising a third pull up device coupled between the drain of the first GaN-based transistor and the power supply.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNMENT DOCUMENTS AND THE RECEIVING PARTY'S POSTAL CODE PREVIOUSLY RECORDED AT REEL: 053864 FRAME: 0208. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 9, 2021
From: NAVITAS SEMICONDUCTOR, INC.
To: NAVITAS SEMICONDUCTOR LIMITED
Reel/Frame 056758/0314 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 23, 2020
From: NAVITAS SEMICONDUCTOR, INC.
To: NAVITAS SEMICONDUCTOR LIMITED
Reel/Frame 053864/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 4, 2019
From: KINZER, DANIEL M.; SHARMA, SANTOSH; ZHANG, JU JASON
To: NAVITAS SEMICONDUCTOR, INC.
Reel/Frame 047908/0117 →
Continuity (4)
Continuation 14667523 · Mar 24, 2015
Provisional Application 62127725 · Mar 3, 2015
Provisional Application 62051160 · Sep 16, 2014
Related Publication 20160336926A1 · Nov 17, 2016
Cited By (2)
US 12,341,373 US 12,355,435