Nonvolatile memory devices relating to operation ranges
View Patent ↗A nonvolatile memory device may include a nonvolatile memory cell and a sensing circuit. The sensing circuit is coupled to a bit line of the nonvolatile memory cell. The sensing circuit may be realized using an inverter comprised of a P-channel transistor coupled to a supply voltage line and an N-channel transistor coupled to a ground voltage. The gate of the P-channel transistor is coupled to the ground voltage.
1. A nonvolatile memory (NVM) device comprising:
a nonvolatile memory cell; and
a sensing circuit coupled to a bit line of the nonvolatile memory cell,
wherein the sensing circuit is realized using an inverter comprised of a P-channel transistor coupled to a supply voltage line and an N-channel transistor coupled to a ground voltage, and
wherein a gate of the P-channel transistor is coupled to the ground voltage, and
wherein a resistance value of the N-channel transistor is less than a resistance value of the P-channel transistor if both the N-channel transistor and the P-channel transistor are turned on.
2. The NVM device of claim 1 , wherein the nonvolatile memory cell is configured to include a cell transistor coupled between the bit line and the ground voltage.
3. The NVM device of claim 1 , wherein the nonvolatile memory cell is configured to include a first P-channel transistor having a drain coupled to the ground voltage, a floating gate, and a source.
4. The NVM device of claim 3 , wherein the nonvolatile memory cell further includes a selection transistor coupled between the bit line and the first P-channel transistor.
5. The NVM device of claim 4 , wherein the selection transistor is realized using a second P-channel transistor having a source coupled to the bit line, a drain coupled to the source of the first P-channel transistor, and a gate to which a first enablement signal is inputted.
6. The NVM device of claim 1 , further comprising a resistive load portion coupled between the bit line and the supply voltage line.
7. The NVM device of claim 6 , wherein the resistive load portion is realized using a third P-channel transistor having a source coupled to the supply voltage line, a drain coupled to the bit line, and a gate to which a second enablement signal is inputted.
8. The NVM device of claim 7 , wherein the third P-channel transistor operates in a linear region or a saturation region according to a voltage level of a supply voltage applied to the supply voltage line and a voltage level of the second enablement signal.
9. The NVM device of claim 7 ,
wherein the resistive load portion further includes a second enablement signal generator configured to generate the second enablement signal; and
wherein a voltage level of the second enablement signal varies according to a supply voltage applied to the supply voltage line.
10. The NVM device of claim 9 ,
wherein the second enablement signal is generated to have a voltage level that allows the third P-channel transistor to operate in a linear region when the supply voltage has a high level; and
wherein the second enablement signal is generated to have a voltage level that allows the third P-channel transistor to operate in a saturation region when the supply voltage has a low level.
11. The NVM device of claim 9 , wherein the second enablement signal is generated from the second enablement signal generator to have a voltage level which is within the range of 30% to 70% of the supply voltage.
12. The NVM device of claim 11 , wherein the second enablement signal is generated to have a voltage level that corresponds to 50% of the supply voltage.
13. The NVM device of claim 9 ,
wherein the second enablement signal generator is realized using a voltage division bias circuit;
wherein the voltage division bias circuit includes a first resistor and a second resistor which are coupled in series between the supply voltage line and the ground voltage; and
wherein the voltage division bias circuit further includes an output line branched from a node between the first and second resistors.
14. The NVM device of claim 13 , wherein the first and second resistors have substantially the same resistance value.
15. The NVM device of claim 1 ,
wherein the N-channel transistor has a gate coupled to a sensing input line connected to the bit line, a source coupled to the ground voltage, and a drain coupled to a sensing output line; and
wherein a source and a drain of the P-channel transistor are coupled to the supply voltage line and the sensing output line, respectively.
16. The NVM device of claim 15 , wherein the N-channel transistor has a transconductance which is higher than a transconductance of the P-channel transistor.
17. The NVM device of claim 16 , wherein a channel length of the N-channel transistor is less than a channel length of the P-channel transistor, or a channel width of the N-channel transistor is greater than a channel width of the P-channel transistor.