Cell library and data for designs
A cell library readable by a computer device includes cell data of a power supply reinforcement cell, specifying a conductive path that connects high-potential power supply routings located on both sides of one low-potential power supply routing with the routing interposed therebetween or low-potential power supply routings located on both sides of one high-potential power supply routing with the routing interposed therebetween, in data of plural cells which is used in designs of a semiconductor device including plural high-potential power supply routings, connected to a high-potential power supply trunk, which are separated from each other and are placed in parallel with each other, plural low-potential power supply routings, connected to a low-potential power supply trunk, which are placed alternately and in parallel with the high-potential power supply routings, and functional circuits which are formed in regions located between the high-potential power supply routings and the low-potential power supply routings.
1. A computer program product comprising a non-transitory computer-readable storage medium containing code which, when executed by one or more processors, performs an operation for generating a design of a semiconductor device,
wherein the design of the semiconductor device comprises, in a semiconductor substrate:
a plurality of high-potential power supply routings connected to a high-potential power supply trunk, the plurality of high-potential power supply routings separated from each other and placed in parallel with each other; and
a plurality of low-potential power supply routings connected to a low-potential power supply trunk, the plurality of low-potential power supply routings placed alternately and in parallel with the plurality of high-potential power supply routings;
wherein the operation for generating a design of a semiconductor device comprises a predefined automatic placement and routing operation comprising:
accessing, from a predefined cell library, first cell data for one or more functional cells corresponding to one or more functional circuits;
arranging the one or more functional circuits in regions located between the high-potential power supply routings and the low-potential power supply routings;
accessing, from the predefined cell library, second cell data for a power supply reinforcement cell; and
arranging the power supply reinforcement cell to form a conductive path comprising a conductive routing that connects two adjacent first power supply routings of one type of high-potential power supply routings and low-potential power supply routings,
wherein a second power supply routing of the other type of the high-potential power supply routings and the low-potential power supply routings is interposed between the two adjacent first power supply routings.
2. The computer program product according to claim 1 , wherein the power supply reinforcement cell has a predetermined width and a predetermined height that is twice a distance between an adjacent high-potential power supply routing and low-potential power supply routing, when seen in a plan view.
3. The computer program product according to claim 2 , wherein the power supply reinforcement cell specifies:
a first power-feeding region which is provided in a first well of a first conductivity type,
a first via that leads from the first power-feeding region through connection to a power supply routing of any one polarity within the low-potential power supply routing or the high-potential power supply routing to an upper routing layer thereof,
a second power-feeding region which is provided in a second well of a first conductivity type formed with a well of a second conductivity type next to the first well interposed therebetween,
a second via that leads from the second power-feeding region through connection to a separate power supply routing of the one polarity to an upper routing layer thereof, and
a power supply reinforcement routing of the one polarity which connects the first via and the second via.
4. The computer program product according to claim 3 , wherein the first conductivity type is an N-type, the second conductivity type is a P-type, and the power supply routing of the one polarity is a high-potential power supply routing.
5. The computer program product according to claim 3 , wherein the first conductivity type is a P-type, the second conductivity type is an N-type, and the power supply routing of the one polarity is a low-potential power supply routing.
6. The computer program product according to claim 2 , wherein the power supply reinforcement cell specifies:
a first via, connected to a power supply routing of any one polarity within a low-potential power supply routing or a high-potential power supply routing, which leads to an upper routing layer thereof,
a second via, connected to a neighboring power supply routing of the same polarity as that of the power supply routing having the first via connected thereto, which leads to an upper routing layer thereof, and
a power supply reinforcement routing of the one polarity which connects the first via and the second via.
7. The computer program product according to claim 6 , wherein the first conductivity type is an N-type, the second conductivity type is a P-type, and the power supply routing of the one polarity is a high-potential power supply routing.
8. The computer program product according to claim 6 , wherein the first conductivity type is a P-type, the second conductivity type is an N-type, and the power supply routing of the one polarity is a low-potential power supply routing.
9. The computer program product according to claim 1 , wherein the power supply reinforcement cell has a predetermined width and a predetermined height that is a distance between an adjacent high-potential power supply routing and low-potential power supply routing, when seen in a plan view,
wherein two power supply reinforcement cells are arranged with line-symmetric placement and defined as one set, wherein the set specifies a conductive routing that connects two adjacent first power supply routings of one type of high-potential power supply routings and low-potential power supply routings,
wherein a second power supply routing of the other type of the high-potential power supply routings and the low-potential power supply routings is interposed between the two adjacent power supply routings.
10. The computer program product according to claim 9 , wherein the power supply reinforcement cell specifies:
a first power-feeding region which is provided in a first well of a first conductivity type,
a first via that leads from the first power-feeding region through connection to a power supply routing of any one polarity within the low-potential power supply routing or the high-potential power supply routing to an upper routing layer thereof, and
a power supply reinforcement routing of the one polarity which is connected to the first via.
11. The computer program product according to claim 10 , wherein the first conductivity type is an N-type, and the power supply routing of the one polarity is a high-potential power supply routing.
12. The computer program product according to claim 10 , wherein the first conductivity type is a P-type, and the power supply routing of the one polarity is a low-potential power supply routing.
13. The computer program product according to claim 9 , wherein the power supply reinforcement cell specifies:
a first via, connected to a power supply routing of any one polarity within a low-potential power supply routing or a high-potential power supply routing, which leads to an upper routing layer thereof, and
a power supply reinforcement routing of the one polarity which is connected to the first via.
14. The computer program product according to claim 13 , wherein the first conductivity type is an N-type, and the power supply routing of the one polarity is a high-potential power supply routing.
15. The computer program product according to claim 13 , wherein the first conductivity type is a P-type, and the power supply routing of the one polarity is a low-potential power supply routing.
16. A computer program product comprising a non-transitory computer-readable storage medium containing code which, when executed by one or more processors, performs an operation for generating a design of a semiconductor device, wherein the design of the semiconductor device comprises, in a semiconductor substrate:
a plurality of high-potential power supply routings connected to a high-potential power supply trunk, the plurality of high-potential power supply routings separated from each other and placed in parallel with each other; and
a plurality of low-potential power supply routings connected to a low-potential power supply trunk, the plurality of low-potential power supply routings placed alternately and in parallel with the plurality of high-potential power supply routings;
wherein the operation for generating a design of a semiconductor device comprises a predefined automatic placement and routing operation comprising:
accessing, from a predefined cell library, first cell data for one or more functional cells corresponding to one or more functional circuits;
arranging the one or more functional circuits in regions located between the high-potential power supply routings and the low-potential power supply routings;
accessing, from the predefined cell library, second cell data for a power supply reinforcement cell having a predetermined width and a predetermined height that is twice a distance between an adjacent high-potential power supply routing and low-potential power supply routing, when seen in a plan view; and
arranging the power supply reinforcement cell to form a conductive path that comprises a conductive routing that connects two adjacent first power supply routings of one type of high-potential power supply routings and low-potential power supply routings,
wherein a second power supply routing of the other type of the high-potential power supply routings and the low-potential power supply routings is interposed between the two adjacent first power supply routings.
17. A semiconductor device comprising:
a semiconductor substrate comprising:
a plurality of high-potential power supply routings coupled with a high-potential power supply trunk, wherein the plurality of high-potential power supply routings are separated from each other and are arranged in parallel with each other;
a plurality of low-potential power supply routings connected to a low-potential power supply trunk, wherein the plurality of low-potential power supply routings are placed alternately and in parallel with the plurality of high-potential power supply routings;
one or more functional circuits formed in regions located between the high-potential power supply routings and the low-potential power supply routings; and
at least one power supply reinforcement element specifying a conductive routing that connects two adjacent first power supply routings of one type of high-potential power supply routings and low-potential power supply routings, wherein a second power supply routing of the other type of the high-potential power supply routings and the low-potential power supply routings is interposed between the two adjacent first power supply routings,
wherein an arrangement of the at least one power supply reinforcement element is determined according to a predefined automatic placement and routing operation in which cell data for the at least one power supply reinforcement element is accessed from a predefined cell library.
18. The semiconductor device of claim 17 , wherein the power supply reinforcement element has a predetermined width and a predetermined height that is twice a distance between an adjacent high-potential power supply routing and low-potential power supply routing, when seen in a plan view.
19. The semiconductor device of claim 17 , wherein the power supply reinforcement element has a predetermined width and a predetermined height that is a distance between an adjacent high-potential power supply routing and low-potential power supply routing, when seen in a plan view,
wherein two power supply reinforcement elements are arranged with line-symmetric placement and defined as one set, wherein the set specifies a conductive routing that connects two adjacent first power supply routings of one type of high-potential power supply routings and low-potential power supply routings,
wherein a second power supply routing of the other type of the high-potential power supply routings and the low-potential power supply routings is interposed between the two adjacent power supply routings.
20. The computer program product of claim 1 , wherein accessing the first cell data, arranging the one or more functional circuits, accessing the second cell data, and arranging the power supply reinforcement cell each occur within a first instance of performing the predefined automatic placement and routing operation.