HIGH-VOLTAGE GAN HIGH ELECTRON MOBILITY TRANSISTORS WITH REDUCED LEAKAGE CURRENT
High-voltage, gallium-nitride HEMTs are described that are capable of withstanding reverse-bias voltages of at least 900 V and, in some cases, in excess of 2000 V with low reverse-bias leakage current. A HEMT may comprise a lateral geometry having a gate, a thin insulating layer formed beneath the gate, a gate-connected field plate, and a source-connected field plate.
1 . A high electron-mobility transistor (HEMT) comprising:
a gallium-nitride conduction layer;
a barrier layer formed over the gallium-nitride conduction layer;
a gate, source, and drain formed over the barrier layer;
a first insulating layer formed in regions between the gate and drain and between the gate and source;
a gallium-oxide layer formed between the barrier layer and the gate; and
a gate-connected field plate electrically connected to the gate and extending beyond edges of the gate toward the drain and source over the first insulating layer.
2 . The HEMT of claim 1 , wherein the gallium-oxide layer has a thickness between approximately 1 nm and approximately 5 nm.
3 . The HEMT of claim 2 , further comprising a gallium-nitride cap layer formed between the barrier layer and the gallium-oxide layer.
4 . The HEMT of claim 3 , wherein a thickness of the gallium-nitride cap layer is between approximately 1 nm and approximately 10 nm.
5 . The HEMT of claim 3 , further comprising:
a source-connected field plate comprising a conductor that is electrically connected to the source and extends over the gate; and
a second insulating layer separating the source-connected field plate and the gate.
6 . The HEMT of claim 5 , wherein the source-connected field plate extends beyond the gate-connected field plate toward the drain a distance between approximately 1 micron and approximately 4 microns.
7 . The HEMT of claim 6 , wherein an edge of the source-connected field plate is between approximately 4 microns and approximately 10 microns from an edge of the drain.
8 . The HEMT of claim 5 , wherein a thickness of the first insulating layer is between approximately 25 nm and approximately 200 nm.
9 . The HEMT of claim 5 , wherein a thickness of the second insulating layer is between approximately 300 nm and approximately 600 nm.
10 . The HEMT of claim 5 configured to withstand a reverse-bias voltage of approximately 2000 volts.
11 . The HEMT of claim 10 , wherein a reverse-leakage current at 2000 volts reverse bias is not more than 40 microamps per millimeter of gate width.
12 . The HEMT of claim 10 configured to handle a forward current of 1 amp per millimeter of gate width.
13 . The HEMT of claim 3 , further comprising electrical isolation regions formed adjacent to the source and drain, wherein the electrical isolation regions comprise damaged crystalline semiconductor that includes one or more of the following implanted ion species: nitrogen, phosphorous, boron, and argon.
14 . The HEMT of claim 3 , wherein a length of the gate is between approximately 0.1 micron and approximately 1.5 micron.
15 . The HEMT of claim 14 , wherein edges of the gate are sloped outward between approximately 5 degrees and approximately 60 degrees from vertical.
16 . The HEMT of claim 14 , wherein the gate-connected field plate extends beyond a first edge of the gate toward the drain between approximately 0.3 μm and approximately 0.8 μm, and extends beyond a second edge of the gate toward the source between approximately 0.1 μm and approximately 0.4 μm.
17 . The HEMT of claim 3 , wherein a spacing between an edge of the gate and an edge of the drain is between approximately 5 microns and approximately 20 microns.
18 . The HEMT of claim 3 , wherein the gate length is approximately 0.15 micron, and the HEMT is configured to drive currents up to 1 amp/mm at modulation rates as high as 30 GHz.
19 . A high electron-mobility transistor (HEMT) comprising:
a gallium-nitride conduction layer;
a barrier layer formed over the gallium-nitride conduction layer;
a gate, source, and drain formed over the barrier layer;
a first insulating layer formed in regions between the gate and drain and between the gate and source;
a gate insulating layer having a thickness between approximately 1 nm and approximately 5 nm formed between the barrier layer and the gate; and
a gate-connected field plate electrically connected to the gate and extending beyond edges of the gate toward the drain and source over the first insulating layer.
20 . The HEMT of claim 19 , further comprising:
a source-connected field plate comprising a conductor that is electrically connected to the source and extends over the gate; and
a second insulating layer separating the source-connected field plate and the gate.
21 . The HEMT of claim 20 , wherein the source-connected field plate extends beyond the gate-connected field plate toward the drain a distance between approximately 1 micron and approximately 4 microns.
22 . The HEMT of claim 21 , wherein an edge of the source-connected field plate is between approximately 4 microns and approximately 10 microns from an edge of the drain.
23 . The HEMT of claim 20 , wherein a thickness of the first insulating layer is between approximately 25 nm and approximately 200 nm.
24 . The HEMT of claim 20 , wherein a thickness of the second insulating layer is between approximately 300 nm and approximately 600 nm.
25 . The HEMT of claim 20 configured to withstand a reverse-bias voltage of approximately 2000 volts.
26 . The HEMT of claim 25 , wherein a reverse-leakage current at 2000 volts reverse bias is not more than 40 microamps per millimeter of gate width.
27 . The HEMT of claim 25 configured to handle a forward current of 1 amp per millimeter of gate width.
28 . The HEMT of claim 19 , wherein the gate insulating layer comprises gallium-oxide.
29 . A method for making a high electron-mobility transistor (HEMT), the method comprising:
forming a gallium-nitride conduction layer on a substrate;
forming a barrier layer adjacent to the gallium-nitride conduction layer;
forming a first source and a drain spaced apart and in electrical contact with the conduction layer;
forming a gate adjacent to the barrier layer between the source and the drain; and
forming a gallium-oxide layer between the gate and the barrier layer.
30 . The method of claim 29 , wherein forming the gallium-oxide layer comprises:
opening a via to expose a region of a gallium-nitride layer at the location of the gate prior to forming the gate; and
subjecting the exposed region to an oxygen plasma for a period of time.
31 . The method of claim 30 , wherein the period of time is between approximately 10 seconds and approximately 120 seconds.
32 . The method of claim 30 , further comprising maintaining a pressure between approximately 0.5 Torr and approximately 3 Torr while subjecting the exposed region to the oxygen plasma.
33 . The method of claim 30 , further comprising forming a gallium-nitride cap layer between the barrier layer and the source and drain, wherein the gallium-oxide layer is formed from the gallium-nitride cap layer.
34 . The method of claim 30 , further comprising:
forming a first insulating layer that extends between the source and gate and the gate and drain; and
forming a gate-connected field plate in electrical contact with the gate that extends beyond outer edges of the gate toward the source and drain.
35 . The method of claim 34 , further comprising:
forming a second insulating layer that extends over the gate and gate-connected field plate; and
forming a source-connected field plate in electrical contact with the source that extends beyond the gate toward the drain.
36 . The method of claim 30 , further comprising implanting ions into the conduction layer to damage the conduction layer and form electrical isolation regions adjacent to the source and the drain.